A wafer-level three dimensional chip stacking technology for high-performance microelectronics and MEMS

K. T. Park, K. W. Lee, Y. Igarashi, Y. Yamada, H. Kurino, T. Nakamura, T. Morooka, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution


This paper presents a wafer-level three dimensional (3D) chips stacking technology for high performance microelectronics and MEMS. The stacked chips, which are composed of homo- or heterogeneous sub-system, are electrically connected with short vertical interconnections through the chips. This technology provides many advantages such as compact overall system size, low power, highly design flexibility, high level of integration and interconnectivity, and massively parallel processing. By using this technology, ultra-high density memory, massive parallel processor and high performance embedded electronics can be realized with a single stacked chip. This technology can be also used for micro-electro-mechanical system (MEMS) which consists of multi-devices such as sensors, actuators and microsystems containing the components for a complete system or subsystem. In order to realize such 3D stacked chips, we have developed a wafer-level chip stacking technology fully compatible with standard CMOS process. Using this technology, 3D stacked image sensor test chip was fabricated and successfully demonstrated their functions.

Original languageEnglish
Title of host publicationAdvances in Electronic Packaging; Manufacturing, Microelectronics Systems Systems and Exploratory Topics, Optoelectronics and Photonic Packaging
Number of pages5
Publication statusPublished - 2001
EventAdvances in Electronic Packaging - Kauai, Hi, United States
Duration: 2001 Jul 82001 Jul 13

Publication series

NameAdvances in Electronic Packaging


OtherAdvances in Electronic Packaging
Country/TerritoryUnited States
CityKauai, Hi

ASJC Scopus subject areas

  • Engineering(all)
  • Electrical and Electronic Engineering


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