A wafer-level three dimensional chip stacking technology for high-performance microelectronics and MEMS

This paper presents a wafer-level three dimensional (3D) chips stacking technology for high performance microelectronics and MEMS. The stacked chips, which are composed of homo- or heterogeneous sub-system, are electrically connected with short vertical interconnections through the chips. This technology provides many advantages such as compact overall system size, low power, highly design flexibility, high level of integration and interconnectivity, and massively parallel processing. By using this technology, ultra-high density memory, massive parallel processor and high performance embedded electronics can be realized with a single stacked chip. This technology can be also used for micro-electro-mechanical system (MEMS) which consists of multi-devices such as sensors, actuators and microsystems containing the components for a complete system or subsystem. In order to realize such 3D stacked chips, we have developed a wafer-level chip stacking technology fully compatible with standard CMOS process. Using this technology, 3D stacked image sensor test chip was fabricated and successfully demonstrated their functions.