A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching

Yitao Ma, Tetsuo Endoh, Tadashi Shibata

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A vertical-MOSFET-based digital core circuit with vector matching function is proposed for achieving high-speed and low-power operation. The circuit designs with both planar and vertical MOSFET model are performed under 180nm CMOS technology, and the circuit operation is verified by NanoSim hardware simulation. Comparing with the conventional planar MOSFET case, the power consumption of the vertical MOSFET based circuit achieves more than 30% reduction without dependence on operating frequency. Furthermore, as circuit delay time can be suppressed, the vertical MOSFET based circuit also achieves the much higher maximum operating frequency than the planar MOSFET case up to 360MHz under the exactly same simulation conditions. This proposed core circuit can be flexibly utilized not only as an independent vector matching circuit but also as a unit circuit in the multi-core vector matching system.

Original languageEnglish
Title of host publication2011 International SoC Design Conference, ISOCC 2011
Pages203-206
Number of pages4
Publication statusPublished - 2011 Dec 1
Event8th International SoC Design Conference 2011, ISOCC 2011 - Jeju, Korea, Republic of
Duration: 2011 Nov 172011 Nov 18

Publication series

Name2011 International SoC Design Conference, ISOCC 2011

Other

Other8th International SoC Design Conference 2011, ISOCC 2011
CountryKorea, Republic of
CityJeju
Period11/11/1711/11/18

Keywords

  • High-speed
  • Low-Pwer
  • SIMD
  • Vector matcihng
  • Vertical MOSFET

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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