A two-bit-per-cell Content-Addressable Memory using Single-Electron Transistors

Katsuhiko Degawa; Takafumi Aoki; Hiroshi Inokawa; Tatsuo Higuchi; Yasuo Takahashi

A two-bit-per-cell Content-Addressable Memory using Single-Electron Transistors

Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi

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Research output: Contribution to journal › Conference article › peer-review

8 Citations (Scopus)

Abstract

This paper presents a circuit design of a two-bit-percell Content-Addressable Memory (CAM) using Single-Electron Transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based static memory cell and (ii) four-level data matching function employing periodic drain-current characteristics of SETs with dynamic phase-shift control. A simple multi-gate SET can be used to realize four-level data matching within a compact CAM cell circuit. As a result, the proposed two-bit-per-cell CAM architecture reduces the number of transistors to 1/3 compared with the conventional CAM architecture.

Original language	English
Pages (from-to)	32-38
Number of pages	7
Journal	Proceedings of The International Symposium on Multiple-Valued Logic
Publication status	Published - 2005 Sept 20
Event	35th International Symposium on Multiple-Valued Logic, ISMVL 2005 - Calgary, Alta., Canada Duration: 2005 May 19 → 2005 May 21

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

Cite this

@article{0dd89f9d976b47b09ebaa0f72754208d,

title = "A two-bit-per-cell Content-Addressable Memory using Single-Electron Transistors",

abstract = "This paper presents a circuit design of a two-bit-percell Content-Addressable Memory (CAM) using Single-Electron Transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based static memory cell and (ii) four-level data matching function employing periodic drain-current characteristics of SETs with dynamic phase-shift control. A simple multi-gate SET can be used to realize four-level data matching within a compact CAM cell circuit. As a result, the proposed two-bit-per-cell CAM architecture reduces the number of transistors to 1/3 compared with the conventional CAM architecture.",

author = "Katsuhiko Degawa and Takafumi Aoki and Hiroshi Inokawa and Tatsuo Higuchi and Yasuo Takahashi",

year = "2005",

month = sep,

day = "20",

language = "English",

pages = "32--38",

journal = "Proceedings of The International Symposium on Multiple-Valued Logic",

issn = "0195-623X",

publisher = "IEEE Computer Society",

note = "35th International Symposium on Multiple-Valued Logic, ISMVL 2005 ; Conference date: 19-05-2005 Through 21-05-2005",

}

TY - JOUR

T1 - A two-bit-per-cell Content-Addressable Memory using Single-Electron Transistors

AU - Degawa, Katsuhiko

AU - Aoki, Takafumi

AU - Inokawa, Hiroshi

AU - Higuchi, Tatsuo

AU - Takahashi, Yasuo

PY - 2005/9/20

Y1 - 2005/9/20

N2 - This paper presents a circuit design of a two-bit-percell Content-Addressable Memory (CAM) using Single-Electron Transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based static memory cell and (ii) four-level data matching function employing periodic drain-current characteristics of SETs with dynamic phase-shift control. A simple multi-gate SET can be used to realize four-level data matching within a compact CAM cell circuit. As a result, the proposed two-bit-per-cell CAM architecture reduces the number of transistors to 1/3 compared with the conventional CAM architecture.

AB - This paper presents a circuit design of a two-bit-percell Content-Addressable Memory (CAM) using Single-Electron Transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based static memory cell and (ii) four-level data matching function employing periodic drain-current characteristics of SETs with dynamic phase-shift control. A simple multi-gate SET can be used to realize four-level data matching within a compact CAM cell circuit. As a result, the proposed two-bit-per-cell CAM architecture reduces the number of transistors to 1/3 compared with the conventional CAM architecture.

UR - http://www.scopus.com/inward/record.url?scp=24644507546&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=24644507546&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:24644507546

SN - 0195-623X

SP - 32

EP - 38

JO - Proceedings of The International Symposium on Multiple-Valued Logic

JF - Proceedings of The International Symposium on Multiple-Valued Logic

T2 - 35th International Symposium on Multiple-Valued Logic, ISMVL 2005

Y2 - 19 May 2005 through 21 May 2005

ER -

A two-bit-per-cell Content-Addressable Memory using Single-Electron Transistors

Abstract

ASJC Scopus subject areas

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