This paper presents a circuit design of a two-bit-percell Content-Addressable Memory (CAM) using Single-Electron Transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based static memory cell and (ii) four-level data matching function employing periodic drain-current characteristics of SETs with dynamic phase-shift control. A simple multi-gate SET can be used to realize four-level data matching within a compact CAM cell circuit. As a result, the proposed two-bit-per-cell CAM architecture reduces the number of transistors to 1/3 compared with the conventional CAM architecture.
|Number of pages||7|
|Journal||Proceedings of The International Symposium on Multiple-Valued Logic|
|Publication status||Published - 2005 Sept 20|
|Event||35th International Symposium on Multiple-Valued Logic, ISMVL 2005 - Calgary, Alta., Canada|
Duration: 2005 May 19 → 2005 May 21
ASJC Scopus subject areas
- Computer Science(all)