A two-bit-per-cell Content-Addressable Memory using Single-Electron Transistors

Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi

Research output: Contribution to journalConference articlepeer-review

8 Citations (Scopus)

Abstract

This paper presents a circuit design of a two-bit-percell Content-Addressable Memory (CAM) using Single-Electron Transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based static memory cell and (ii) four-level data matching function employing periodic drain-current characteristics of SETs with dynamic phase-shift control. A simple multi-gate SET can be used to realize four-level data matching within a compact CAM cell circuit. As a result, the proposed two-bit-per-cell CAM architecture reduces the number of transistors to 1/3 compared with the conventional CAM architecture.

Original languageEnglish
Pages (from-to)32-38
Number of pages7
JournalProceedings of The International Symposium on Multiple-Valued Logic
Publication statusPublished - 2005 Sep 20
Event35th International Symposium on Multiple-Valued Logic, ISMVL 2005 - Calgary, Alta., Canada
Duration: 2005 May 192005 May 21

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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