A Ta/Mo interdiffusion gate technology for dual metal gate-first FinFET fabrication

T. Matsukawa, Kazuhiko Endo, Y. X. Liu, S. O'Uchi, Y. Ishikawa, H. Yamauchi, J. Tsukada, K. Ishii, M. Masahara, K. Sakamoto, E. Suzuki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

The Ta/Mo interdiffusion gate technology was introduced into the gate-first FinFET process. The Ta/Mo gated n-MOS and the Mo gated p-MOS FinFET exhibited symmetrical Vth (0.31/-0.36 V), and the scalability down to 100 nm was demonstrated.

Original languageEnglish
Title of host publication2007 IEEE International SOI Conference Proceedings
Pages143-144
Number of pages2
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event2007 IEEE International Systems-on-Chip Conference, SOI - Indian Wells, CA, United States
Duration: 2007 Oct 12007 Oct 4

Other

Other2007 IEEE International Systems-on-Chip Conference, SOI
CountryUnited States
CityIndian Wells, CA
Period07/10/107/10/4

ASJC Scopus subject areas

  • Engineering(all)

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