A systolic memory architecture for fast codebook design based on MMPDCL algorithm

Kentaro Sano, Chiaki Takagi, Ryusuke Egawa, Kenichi Suzuki, Tadao Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Vector quantization with an adaptive codebook is attractive for lossy data compression. During the last few decades, architectures have been proposed to accelerate adaptive codebook design that requires a huge amount of computation. However, they are mainly based on Kohonen competitive learning algorithm or LBG algorithm that have an essential problem, the under-utilization problem. This paper presents a systolic memory architecture for high-speed codebook design based on MMPDCL algorithm not suffering from the under-utilization problem. We modify MMPDCL algorithm to exploit parallelism and implement with simple hardware. Simulation results demonstrated that the modified MMPDCL algorithm can give codebooks with comparable MSEs to the original MMPDCL algorithm.

Original languageEnglish
Title of host publicationInternational Conferen ON Information Technology
Subtitle of host publicationCoding Computing, ITCC 2004
EditorsP.K. Srimani, A. Abraham, M. Cannataro, J. Domingo-Ferrer, R. Hashemi
Pages572-578
Number of pages7
DOIs
Publication statusPublished - 2004 Jul 7
EventInternational Conference on Information Technology: Coding Computing, ITCC 2004 - Las Vegas, NV, United States
Duration: 2004 Apr 52004 Apr 7

Publication series

NameInternational Conference on Information Technology: Coding Computing, ITCC
Volume1

Other

OtherInternational Conference on Information Technology: Coding Computing, ITCC 2004
CountryUnited States
CityLas Vegas, NV
Period04/4/504/4/7

Keywords

  • Codebook design
  • MMPDCL algorithm
  • Systolic memory architecture
  • Vector quantization

ASJC Scopus subject areas

  • Software
  • Information Systems
  • Engineering(all)

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  • Cite this

    Sano, K., Takagi, C., Egawa, R., Suzuki, K., & Nakamura, T. (2004). A systolic memory architecture for fast codebook design based on MMPDCL algorithm. In P. K. Srimani, A. Abraham, M. Cannataro, J. Domingo-Ferrer, & R. Hashemi (Eds.), International Conferen ON Information Technology: Coding Computing, ITCC 2004 (pp. 572-578). (International Conference on Information Technology: Coding Computing, ITCC; Vol. 1). https://doi.org/10.1109/ITCC.2004.1286525