TY - GEN
T1 - A Systematic Design of Tamper-Resistant Galois-Field Arithmetic Circuits Based on Threshold Implementation with (d + 1) Input Shares
AU - Ueno, Rei
AU - Homma, Naofumi
AU - Aoki, Takafumi
N1 - Publisher Copyright:
© 2017 IEEE.
Copyright:
Copyright 2017 Elsevier B.V., All rights reserved.
PY - 2017/6/30
Y1 - 2017/6/30
N2 - This paper presents a systematic design of tamper-resistant Galois-Field (GF) arithmetic circuits based on Threshold Implementation (TI) where a secret variable is represented withmultiple variables, called shares, given by random numbers. TI isone of the countermeasures against Differential Power Analysis(DPA) on cryptographic hardware. The security order of TIdepends on the number of shares. The minimum number ofshares to be resistant dth-order DPA is said to be (d+1). Whilethe construction of GF arithmetic circuits of quadratic functionbased on TI with (d + 1) shares is known, it is not known howto construct other types of circuits based on it. In this paper, wepresent a generalization and systematic method of constructingthe TI with (d + 1) input shares for any kind of GF arithmeticcircuit in order to design a larger variety of tamper-resistantGF arithmetic circuits. We then apply the proposed method toa cryptographic hardware design in order to demonstrate its efficiency.
AB - This paper presents a systematic design of tamper-resistant Galois-Field (GF) arithmetic circuits based on Threshold Implementation (TI) where a secret variable is represented withmultiple variables, called shares, given by random numbers. TI isone of the countermeasures against Differential Power Analysis(DPA) on cryptographic hardware. The security order of TIdepends on the number of shares. The minimum number ofshares to be resistant dth-order DPA is said to be (d+1). Whilethe construction of GF arithmetic circuits of quadratic functionbased on TI with (d + 1) shares is known, it is not known howto construct other types of circuits based on it. In this paper, wepresent a generalization and systematic method of constructingthe TI with (d + 1) input shares for any kind of GF arithmeticcircuit in order to design a larger variety of tamper-resistantGF arithmetic circuits. We then apply the proposed method toa cryptographic hardware design in order to demonstrate its efficiency.
KW - cryptographic hardware
KW - differential power analysis
KW - side-channel analysis
KW - threshold implementation
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U2 - 10.1109/ISMVL.2017.35
DO - 10.1109/ISMVL.2017.35
M3 - Conference contribution
AN - SCOPUS:85026788919
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 136
EP - 141
BT - Proceedings - 2017 IEEE 47th International Symposium on Multiple-Valued Logic, ISMVL 2017
PB - IEEE Computer Society
T2 - 47th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2017
Y2 - 22 May 2017 through 24 May 2017
ER -