A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware

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Abstract

This article proposes a formal design system for automatically generating provably secure register transfer level description of cryptographic hardware based on generalized masking scheme. To address the above problems, we propose a formal design and verification method for generalized masking schem (GMS)-based Galois-field (GF) arithmetic circuits. The proposed method is based on a formal approach to describing and verifying GF arithmetic circuits. The basic ideas revolve around the description of GF arithmetic circuits using a high-level mathematical graph called GF arithmetic circuit graph (GF-ACG) and its verification using an algebraic procedure based on a GroÄbner basis (GB) and a polynomial reduction technique. The proposed methodology automatically generates the GMS-based GF arithmetic circuits from circuit function and GMS order, and then its functionality is verified on the basis of GF-ACG.

Original languageEnglish
Article number9367223
Pages (from-to)84-92
Number of pages9
JournalIEEE Design and Test
Volume38
Issue number3
DOIs
Publication statusPublished - 2021 Jun

Keywords

  • Cryptographic hardware
  • Differential power analysis
  • Formal verification
  • Galois-field arithmetic circuit
  • Masking
  • and Side-channel attack

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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