This paper presents a unified representation of fast addition algorithms based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe and analyze various adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures that can be handled by CTDs include Redundant-Binary (RB) adders, Signed-Digit (SD) adders, Positive-Digit (PD) adders, carry-save adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. In this paper, we focus on an application of CTDs to the analysis of two-operand RB adders with limited carry propagation. The analysis result shows that there exists possible two types of 3-stage CTDs for the RB adders. From this result, we can confirm that well-known RB adders are classified into one of the two types.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 2004 Sep 6|
|Event||2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada|
Duration: 2004 May 23 → 2004 May 26
ASJC Scopus subject areas
- Electrical and Electronic Engineering