A switch block architecture for multi-context FPGAs based on a ferroelectric-capacitor functional pass-gate using multiple/binary valued hybrid signals

Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Dynamically Programmable Gate Arrays (DPGAs) provide more area-efficient implementations than conventional Field Programmable Gate Arrays (FPGAs). One of typical DPGA architectures is multi-context architecture. An DPGA based on multi-context architecture is Multi-Context FPGA (MC-FPGA) which achieves fast switching between contexts. The problem of the conventional SRAM-based MC-FPGA is its large area and standby power dissipation because of the large number of configuration memory bits. Moreover, since SRAM is volatile, the SRAM-based multi-context FPGA is difficult to implement power-gating for standby power reduction. This paper presents an area-efficient and nonvolatile multi-context switch block architecture for MC-FPGAs based on a ferroelectric-capacitor functional pass-gate which merges a multiplevalued threshold function and a nonvolatile multiple-valued storage. The test chip for four contexts is fabricated in a 0.35 μm-CMOS/0.60 μmferroelectric-capacitor process. The transistor count of the proposed multicontext switch block is reduced to 63% in comparison with that of the SRAM-based one.

Original languageEnglish
Pages (from-to)2134-2144
Number of pages11
JournalIEICE Transactions on Information and Systems
VolumeE93-D
Issue number8
DOIs
Publication statusPublished - 2010 Aug

Keywords

  • Dynamically programmable gate array
  • Logic-in-memory circuit
  • Multi-context switch
  • Multiple-valued threshold logic
  • Non-destructive operation
  • Nonvolatile storage

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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