A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs

K. Sunouchi; H. Takato; N. Okabe; T. Yamada; T. Ozaki; S. Inoue; K. Hashimoto; K. Hieda; A. Nitayama; F. Horiguchi; F. Masuoka

A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs

K. Sunouchi, H. Takato, N. Okabe, T. Yamada, T. Ozaki, S. Inoue, K. Hashimoto, K. Hieda, A. Nitayama, F. Horiguchi, F. Masuoka

Center for Innovative Integrated Electronic Systems (CIES)

Research output: Contribution to journal › Conference article › peer-review

51 Citations (Scopus)

Abstract

A novel three-dimensional memory cell called the surrounding gate transistor (SGT) cell has been developed for 64/256-Mb DRAMs (dynamic RAMs). In the SGT cell structure, a transfer gate and a capacitor electrode surround a pillar silicon island. Contact of the bit line is made on top of the silicon pillar. All devices for a memory cell are located in one silicon pillar. Each silicon pillar is isolated by matrixlike trenches. Therefore, there is no intercell leakage current even in small cell-to-cell spacing. The SGT cell can achieve an extremely small cell size of 1.2 μm² and a large capacitance of 30 fF using a relaxed design rule of 0.5 μm. The cell has been fabricated and its functionality confirmed.

Original language	English
Pages (from-to)	23-26
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 1989 Dec 1
Event	1989 International Electron Devices Meeting - Technical Digest - Washington, DC, USA Duration: 1989 Dec 3 → 1989 Dec 6

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

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title = "A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs",

abstract = "A novel three-dimensional memory cell called the surrounding gate transistor (SGT) cell has been developed for 64/256-Mb DRAMs (dynamic RAMs). In the SGT cell structure, a transfer gate and a capacitor electrode surround a pillar silicon island. Contact of the bit line is made on top of the silicon pillar. All devices for a memory cell are located in one silicon pillar. Each silicon pillar is isolated by matrixlike trenches. Therefore, there is no intercell leakage current even in small cell-to-cell spacing. The SGT cell can achieve an extremely small cell size of 1.2 μm2 and a large capacitance of 30 fF using a relaxed design rule of 0.5 μm. The cell has been fabricated and its functionality confirmed.",

author = "K. Sunouchi and H. Takato and N. Okabe and T. Yamada and T. Ozaki and S. Inoue and K. Hashimoto and K. Hieda and A. Nitayama and F. Horiguchi and F. Masuoka",

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language = "English",

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journal = "Technical Digest - International Electron Devices Meeting",

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T1 - A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs

AU - Sunouchi, K.

AU - Takato, H.

AU - Okabe, N.

AU - Yamada, T.

AU - Ozaki, T.

AU - Inoue, S.

AU - Hashimoto, K.

AU - Hieda, K.

AU - Nitayama, A.

AU - Horiguchi, F.

AU - Masuoka, F.

PY - 1989/12/1

Y1 - 1989/12/1

N2 - A novel three-dimensional memory cell called the surrounding gate transistor (SGT) cell has been developed for 64/256-Mb DRAMs (dynamic RAMs). In the SGT cell structure, a transfer gate and a capacitor electrode surround a pillar silicon island. Contact of the bit line is made on top of the silicon pillar. All devices for a memory cell are located in one silicon pillar. Each silicon pillar is isolated by matrixlike trenches. Therefore, there is no intercell leakage current even in small cell-to-cell spacing. The SGT cell can achieve an extremely small cell size of 1.2 μm2 and a large capacitance of 30 fF using a relaxed design rule of 0.5 μm. The cell has been fabricated and its functionality confirmed.

AB - A novel three-dimensional memory cell called the surrounding gate transistor (SGT) cell has been developed for 64/256-Mb DRAMs (dynamic RAMs). In the SGT cell structure, a transfer gate and a capacitor electrode surround a pillar silicon island. Contact of the bit line is made on top of the silicon pillar. All devices for a memory cell are located in one silicon pillar. Each silicon pillar is isolated by matrixlike trenches. Therefore, there is no intercell leakage current even in small cell-to-cell spacing. The SGT cell can achieve an extremely small cell size of 1.2 μm2 and a large capacitance of 30 fF using a relaxed design rule of 0.5 μm. The cell has been fabricated and its functionality confirmed.

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M3 - Conference article

AN - SCOPUS:0024870892

SN - 0163-1918

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JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - 1989 International Electron Devices Meeting - Technical Digest

Y2 - 3 December 1989 through 6 December 1989

ER -

A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs

Abstract

ASJC Scopus subject areas

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