A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs

K. Sunouchi, H. Takato, N. Okabe, T. Yamada, T. Ozaki, S. Inoue, K. Hashimoto, K. Hieda, A. Nitayama, F. Horiguchi, F. Masuoka

Research output: Contribution to journalConference article

47 Citations (Scopus)

Abstract

A novel three-dimensional memory cell called the surrounding gate transistor (SGT) cell has been developed for 64/256-Mb DRAMs (dynamic RAMs). In the SGT cell structure, a transfer gate and a capacitor electrode surround a pillar silicon island. Contact of the bit line is made on top of the silicon pillar. All devices for a memory cell are located in one silicon pillar. Each silicon pillar is isolated by matrixlike trenches. Therefore, there is no intercell leakage current even in small cell-to-cell spacing. The SGT cell can achieve an extremely small cell size of 1.2 μm2 and a large capacitance of 30 fF using a relaxed design rule of 0.5 μm. The cell has been fabricated and its functionality confirmed.

Original languageEnglish
Pages (from-to)23-26
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1989 Dec 1
Event1989 International Electron Devices Meeting - Technical Digest - Washington, DC, USA
Duration: 1989 Dec 31989 Dec 6

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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    Sunouchi, K., Takato, H., Okabe, N., Yamada, T., Ozaki, T., Inoue, S., Hashimoto, K., Hieda, K., Nitayama, A., Horiguchi, F., & Masuoka, F. (1989). A surrounding gate transistor (SGT) cell for 64/256 Mbit DRAMs. Technical Digest - International Electron Devices Meeting, 23-26.