A sub-10-ns 16 × 16 multiplier using 0.6-µm CMOS technology

Yukihito Oowaki, Kenji Numata, Kenji Tsuchiya, Kazushi Tsuda, Hiroshi Takato, Naoko Takenouchi, Akihiro Nitayama, Takayuki Kobayashi, Masahiko Chiba, Shigeyoshi Watanabe, Kazunori Ohuchi, Akimichi Hojo

Research output: Chapter in Book/Report/Conference proceedingChapter


A 16 × 16-bit parallel multiplier fabricated in a 0.6-µm CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth’s algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-µm CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.

Original languageEnglish
Title of host publicationComputer Arithmetic
Subtitle of host publicationVolume II
PublisherWorld Scientific Publishing Co.
Number of pages1
ISBN (Electronic)9789814641470
ISBN (Print)9789814641463
Publication statusPublished - 2015 Jan 1

ASJC Scopus subject areas

  • Computer Science(all)
  • Engineering(all)
  • Mathematics(all)


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