A study on design of PLL for low phase-noise characteristics

Hideyasu Hobara, Yoshiki Kayano, Hiroshi Inoue

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

An UWB RF system can be used in the area of signal processing. Phase Locked Loop (PLL) is one of the important key technologies for broadband communication and signal processing. The phase-noise of output voltage of the oscillator with PLL should be suppressed for the performance. The low phase-noise characteristics as well as the broadband and high-frequency use are very important factor for the UWB application. This study reveals basic considerations for low phase-noise PLL. In order to develop a low phase-noise PLL, we newly attempt to establish a method for designing the phase comparator with high sensitivity. A phase comparator is consisted of XOR with CMOS transistor. The W (Channel Width)/L (Channel Length) ratio related to the delay of CMOS transistor in the phase comparator was designed to improve the sensitivity. As ratio of size of each stage decreases, detection sensitivity increases. Especially, the improvement effect of the W/L ratios of the MOS transistor in 2nd and 3rd stage on detection sensitivity is significant. The proposed phase comparator is built into PLL. It is demonstrated by circuit simulation that the proposed phase comparator has a possibility for improving phase-noise of the PLL.

Original languageEnglish
Title of host publication2012 Proceedings of SICE Annual Conference, SICE 2012
PublisherSociety of Instrument and Control Engineers (SICE)
Pages1416-1421
Number of pages6
ISBN (Print)9781467322591
Publication statusPublished - 2012
Event2012 51st Annual Conference on of the Society of Instrument and Control Engineers of Japan, SICE 2012 - Akita, Japan
Duration: 2012 Aug 202012 Aug 23

Publication series

NameProceedings of the SICE Annual Conference

Other

Other2012 51st Annual Conference on of the Society of Instrument and Control Engineers of Japan, SICE 2012
CountryJapan
CityAkita
Period12/8/2012/8/23

Keywords

  • Low Phase-Noise
  • Phase Comparator
  • Phase Locked Loop(PLL)
  • Sensitivity

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Computer Science Applications
  • Electrical and Electronic Engineering

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