A study of highly scalable DG-FinDRAM

E. Yoshida, T. Miyashita, T. Tanaka

Research output: Contribution to journalArticlepeer-review

21 Citations (Scopus)

Abstract

This letter reports the scalability of a capacitor-less 1T-DRAM, and proposes a new concept about extending the use of 1T-DRAM to gate lengths of less than 50 nm. Superior characteristics such as long retention time and large sense margin even for gate lengths around 50 nm can be obtained with a double-gate fully depleted FinFET DRAM. Considering capacity, speed, power, and structural complexity of embedded memory, the capacitor-less 1T-DRAM has the possibility of playing the leading role among other memories.

Original languageEnglish
Pages (from-to)655-657
Number of pages3
JournalIEEE Electron Device Letters
Volume26
Issue number9
DOIs
Publication statusPublished - 2005 Sep
Externally publishedYes

Keywords

  • DRAM
  • Double-gate (DG) MOSFET
  • Embedded memory
  • FinFET
  • Floating-body effect
  • Silicon-on-insulator (SOI)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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