A still image encoder based on adaptive resolution vector quantization realizing compression ratio over 1/200 featuring needless calculation elimination architecture

M. Fujibayashi; T. Nozawa; T. Nakayama; K. Mochizuki; M. Konda; Koji Kotani; Shigetoshi Sugawa; T. Ohmi

A still image encoder based on adaptive resolution vector quantization realizing compression ratio over 1/200 featuring needless calculation elimination architecture

M. Fujibayashi, T. Nozawa, T. Nakayama, K. Mochizuki, M. Konda, Koji Kotani, Shigetoshi Sugawa, T. Ohmi

Research output: Contribution to conference › Paper › peer-review

Abstract

We have developed an advanced vector quantization (VQ) encoding hardware for still image encoding systems. By utilizing needless calculation elimination method, computational cost of VQ encoding is reduced to 40% or less, while maintaining the accuracy of full-search VQ. We have also developed a still image compression algorithm based on adaptive resolution VQ (AR-VQ), which realizes compression ratio over 1/200 while maintaining image quality. We have successfully implemented these two technologies into a still image encoding processor. The processor can compress still image of 1600 × 2400 pixels within one second, which is 60 times faster than software implementation on current PCs.

Original language	English
Pages	262-265
Number of pages	4
Publication status	Published - 2002 Dec 1
Event	2002 Symposium on VLSI Circuits Digest of Technical Papers - Honolulu, HI, United States Duration: 2002 Jun 13 → 2002 Jun 15

Other

Other	2002 Symposium on VLSI Circuits Digest of Technical Papers
Country/Territory	United States
City	Honolulu, HI
Period	02/6/13 → 02/6/15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Fujibayashi, M., Nozawa, T., Nakayama, T., Mochizuki, K., Konda, M., Kotani, K., Sugawa, S., & Ohmi, T. (2002). A still image encoder based on adaptive resolution vector quantization realizing compression ratio over 1/200 featuring needless calculation elimination architecture. 262-265. Paper presented at 2002 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, United States.

A still image encoder based on adaptive resolution vector quantization realizing compression ratio over 1/200 featuring needless calculation elimination architecture. / Fujibayashi, M.; Nozawa, T.; Nakayama, T.; Mochizuki, K.; Konda, M.; Kotani, Koji; Sugawa, Shigetoshi; Ohmi, T.

2002. 262-265 Paper presented at 2002 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, United States.

Research output: Contribution to conference › Paper › peer-review

Fujibayashi, M, Nozawa, T, Nakayama, T, Mochizuki, K, Konda, M, Kotani, K, Sugawa, S & Ohmi, T 2002, 'A still image encoder based on adaptive resolution vector quantization realizing compression ratio over 1/200 featuring needless calculation elimination architecture', Paper presented at 2002 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, United States, 02/6/13 - 02/6/15 pp. 262-265.

Fujibayashi, M. ; Nozawa, T. ; Nakayama, T. ; Mochizuki, K. ; Konda, M. ; Kotani, Koji ; Sugawa, Shigetoshi ; Ohmi, T. / A still image encoder based on adaptive resolution vector quantization realizing compression ratio over 1/200 featuring needless calculation elimination architecture. Paper presented at 2002 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, HI, United States.4 p.

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AU - Sugawa, Shigetoshi

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A still image encoder based on adaptive resolution vector quantization realizing compression ratio over 1/200 featuring needless calculation elimination architecture

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