A comprehensive statistical model of the switching probability was proposed for a 1Gb spin transfer torque magnetoresistive random access memory (STT-MRAM). Since the switching current varies with every write cycle owing to the thermal instability, the read disturbance and the write error are critical issues in the STT-MRAM. In this paper, the operating condition of read and write was designed so as not to cause the read disturbance or the write error. The effect of an error correcting code (ECC) on the read disturbance was also calculated. Finally, it was demonstrated that the 1Gb STT-MRAM could be realized with the optimal bit line voltages and the ECC.
|Number of pages||9|
|Journal||Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems|
|Publication status||Published - 2008 Dec 1|
|Event||23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2008 - Boston, MA, United States|
Duration: 2008 Oct 1 → 2008 Oct 3
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