A statistical model for assessing the fault tolerance of variable switching currents for a 1Gb spin transfer torque magnetoresistive random access memory

Y. Asao; M. Iwayama; K. Tsuchida; Akihiro Nitayama; H. Yoda; H. Aikawa; S. Ikegawa; T. Kishi

doi:10.1109/DFT.2008.18

A statistical model for assessing the fault tolerance of variable switching currents for a 1Gb spin transfer torque magnetoresistive random access memory

Y. Asao, M. Iwayama, K. Tsuchida, Akihiro Nitayama, H. Yoda, H. Aikawa, S. Ikegawa, T. Kishi

Center for Innovative Integrated Electronic Systems (CIES)

Research output: Contribution to journal › Conference article › peer-review

2 Citations (Scopus)

Abstract

A comprehensive statistical model of the switching probability was proposed for a 1Gb spin transfer torque magnetoresistive random access memory (STT-MRAM). Since the switching current varies with every write cycle owing to the thermal instability, the read disturbance and the write error are critical issues in the STT-MRAM. In this paper, the operating condition of read and write was designed so as not to cause the read disturbance or the write error. The effect of an error correcting code (ECC) on the read disturbance was also calculated. Finally, it was demonstrated that the 1Gb STT-MRAM could be realized with the optimal bit line voltages and the ECC.

Original language	English
Article number	4641210
Pages (from-to)	507-515
Number of pages	9
Journal	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
DOIs	https://doi.org/10.1109/DFT.2008.18
Publication status	Published - 2008 Dec 1
Event	23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2008 - Boston, MA, United States Duration: 2008 Oct 1 → 2008 Oct 3

ASJC Scopus subject areas

Engineering(all)

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10.1109/DFT.2008.18

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Asao, Y., Iwayama, M., Tsuchida, K., Nitayama, A., Yoda, H., Aikawa, H., Ikegawa, S., & Kishi, T. (2008). A statistical model for assessing the fault tolerance of variable switching currents for a 1Gb spin transfer torque magnetoresistive random access memory. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 507-515. [4641210]. https://doi.org/10.1109/DFT.2008.18

A statistical model for assessing the fault tolerance of variable switching currents for a 1Gb spin transfer torque magnetoresistive random access memory. / Asao, Y.; Iwayama, M.; Tsuchida, K.; Nitayama, Akihiro; Yoda, H.; Aikawa, H.; Ikegawa, S.; Kishi, T.

In: Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 01.12.2008, p. 507-515.

Research output: Contribution to journal › Conference article › peer-review

Asao, Y, Iwayama, M, Tsuchida, K, Nitayama, A, Yoda, H, Aikawa, H, Ikegawa, S & Kishi, T 2008, 'A statistical model for assessing the fault tolerance of variable switching currents for a 1Gb spin transfer torque magnetoresistive random access memory', Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 507-515. https://doi.org/10.1109/DFT.2008.18

Asao Y, Iwayama M, Tsuchida K, Nitayama A, Yoda H, Aikawa H et al. A statistical model for assessing the fault tolerance of variable switching currents for a 1Gb spin transfer torque magnetoresistive random access memory. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2008 Dec 1;507-515. 4641210. https://doi.org/10.1109/DFT.2008.18

Asao, Y. ; Iwayama, M. ; Tsuchida, K. ; Nitayama, Akihiro ; Yoda, H. ; Aikawa, H. ; Ikegawa, S. ; Kishi, T. / A statistical model for assessing the fault tolerance of variable switching currents for a 1Gb spin transfer torque magnetoresistive random access memory. In: Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2008 ; pp. 507-515.

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title = "A statistical model for assessing the fault tolerance of variable switching currents for a 1Gb spin transfer torque magnetoresistive random access memory",

abstract = "A comprehensive statistical model of the switching probability was proposed for a 1Gb spin transfer torque magnetoresistive random access memory (STT-MRAM). Since the switching current varies with every write cycle owing to the thermal instability, the read disturbance and the write error are critical issues in the STT-MRAM. In this paper, the operating condition of read and write was designed so as not to cause the read disturbance or the write error. The effect of an error correcting code (ECC) on the read disturbance was also calculated. Finally, it was demonstrated that the 1Gb STT-MRAM could be realized with the optimal bit line voltages and the ECC.",

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AU - Asao, Y.

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AU - Nitayama, Akihiro

AU - Yoda, H.

AU - Aikawa, H.

AU - Ikegawa, S.

AU - Kishi, T.

PY - 2008/12/1

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N2 - A comprehensive statistical model of the switching probability was proposed for a 1Gb spin transfer torque magnetoresistive random access memory (STT-MRAM). Since the switching current varies with every write cycle owing to the thermal instability, the read disturbance and the write error are critical issues in the STT-MRAM. In this paper, the operating condition of read and write was designed so as not to cause the read disturbance or the write error. The effect of an error correcting code (ECC) on the read disturbance was also calculated. Finally, it was demonstrated that the 1Gb STT-MRAM could be realized with the optimal bit line voltages and the ECC.

AB - A comprehensive statistical model of the switching probability was proposed for a 1Gb spin transfer torque magnetoresistive random access memory (STT-MRAM). Since the switching current varies with every write cycle owing to the thermal instability, the read disturbance and the write error are critical issues in the STT-MRAM. In this paper, the operating condition of read and write was designed so as not to cause the read disturbance or the write error. The effect of an error correcting code (ECC) on the read disturbance was also calculated. Finally, it was demonstrated that the 1Gb STT-MRAM could be realized with the optimal bit line voltages and the ECC.

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A statistical model for assessing the fault tolerance of variable switching currents for a 1Gb spin transfer torque magnetoresistive random access memory

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