TY - JOUR
T1 - A statistical model for assessing the fault tolerance of variable switching currents for a 1Gb spin transfer torque magnetoresistive random access memory
AU - Asao, Y.
AU - Iwayama, M.
AU - Tsuchida, K.
AU - Nitayama, Akihiro
AU - Yoda, H.
AU - Aikawa, H.
AU - Ikegawa, S.
AU - Kishi, T.
PY - 2008/12/1
Y1 - 2008/12/1
N2 - A comprehensive statistical model of the switching probability was proposed for a 1Gb spin transfer torque magnetoresistive random access memory (STT-MRAM). Since the switching current varies with every write cycle owing to the thermal instability, the read disturbance and the write error are critical issues in the STT-MRAM. In this paper, the operating condition of read and write was designed so as not to cause the read disturbance or the write error. The effect of an error correcting code (ECC) on the read disturbance was also calculated. Finally, it was demonstrated that the 1Gb STT-MRAM could be realized with the optimal bit line voltages and the ECC.
AB - A comprehensive statistical model of the switching probability was proposed for a 1Gb spin transfer torque magnetoresistive random access memory (STT-MRAM). Since the switching current varies with every write cycle owing to the thermal instability, the read disturbance and the write error are critical issues in the STT-MRAM. In this paper, the operating condition of read and write was designed so as not to cause the read disturbance or the write error. The effect of an error correcting code (ECC) on the read disturbance was also calculated. Finally, it was demonstrated that the 1Gb STT-MRAM could be realized with the optimal bit line voltages and the ECC.
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U2 - 10.1109/DFT.2008.18
DO - 10.1109/DFT.2008.18
M3 - Conference article
AN - SCOPUS:67649982185
SP - 507
EP - 515
JO - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
JF - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
SN - 1550-5774
M1 - 4641210
T2 - 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2008
Y2 - 1 October 2008 through 3 October 2008
ER -