A small-area high performance 512-point 2-dimensional FFT single-chip processor

Naoto Miyamoto, Leo Kaman, Kazuyuki Maruo, Koji Kotani, Tadahiro Ohmi

Research output: Contribution to journalConference article

8 Citations (Scopus)

Abstract

A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource saving multi-datapath radix-22 computation element. The 2-stage CMA, including a pair of single-port SRAMs, is also introduced to speedup the execution time of the 2-dimensional FFTs. Using the above techniques, we have designed an FFT processor core which integrates 552,000 transistors within an area of 2.8 × 2.8 mm2 with CMOS 0.35 μm triple-layer-metal process. This processor can execute a 512-point, 36-bit-complex fixed-point data format, 1-dimensional FFT in 23.2 μsec and a 2-dimensional one in only 23.8 msec at 133 MHz operation.

Original languageEnglish
Article number1257207
Pages (from-to)603-606
Number of pages4
JournalEuropean Solid-State Circuits Conference
DOIs
Publication statusPublished - 2003 Dec 1
Event29th European Solid-State Circuits Conference, ESSCIRC 2003 - Estoril, Portugal
Duration: 2003 Sep 162003 Sep 18

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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