A single-electron-transistor logic gate family and its application - Part II: Design and simulation of a 7-3 parallel counter with linear summation and multiple-valued latch functions

Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Research output: Contribution to journalConference articlepeer-review

10 Citations (Scopus)

Abstract

Guidelines for designing multi-input multi-output counters based on single-electron transistor (SET) logic gate family are presented. A counter consisting of an inverting adder, latched multiple-valued (MV) quantizer, and periodic literals can be made extremely compact owing to the high functionality of SETs and a specific design that utilizes limited kinds of transistors and does not require SETs with control gates or devices for level shifiing. Circuit simulation using a physics-based SET model reveals that the counter operates at a moderately high speed and with ultra-low power consumption.

Original languageEnglish
Pages (from-to)269-274
Number of pages6
JournalProceedings of The International Symposium on Multiple-Valued Logic
Publication statusPublished - 2004 Jul 26
EventProceedings - 34th International Symposium on Multiple-Values Logic, ISMVL 2004 - Toronto, Ont, Canada
Duration: 2004 May 192004 May 22

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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