Guidelines for designing multi-input multi-output counters based on single-electron transistor (SET) logic gate family are presented. A counter consisting of an inverting adder, latched multiple-valued (MV) quantizer, and periodic literals can be made extremely compact owing to the high functionality of SETs and a specific design that utilizes limited kinds of transistors and does not require SETs with control gates or devices for level shifiing. Circuit simulation using a physics-based SET model reveals that the counter operates at a moderately high speed and with ultra-low power consumption.
|Number of pages||6|
|Journal||Proceedings of The International Symposium on Multiple-Valued Logic|
|Publication status||Published - 2004 Jul 26|
|Event||Proceedings - 34th International Symposium on Multiple-Values Logic, ISMVL 2004 - Toronto, Ont, Canada|
Duration: 2004 May 19 → 2004 May 22
ASJC Scopus subject areas
- Computer Science(all)