Abstract
A professional-image-quality video encoder LSI for broadcasting and content distribution has been developed with single-chip 4K 60-fps 4:2:2 high-efficiency video coding (HEVC) encoding capability and 8K ultrahigh definition television scalability. Edge-based intramode pruning and statistically adaptive multiblock-size motion estimation (ME) efficiently reduce HEVC's high computational complexity for real-time processing, while a deeply centralized-mode decision framework maintains high compression performance. Internal reference image caches with 797-Gb/s image feed capability support the 768-GOPS ME computation of distributed motion vector search. Interchip pictures and data exchange features with high-speed data buses are also used for multichip 8K encoding configuration. A subjective evaluation showed that the proposed encoder LSI maintained the same visual quality as an encoder LSI complying with the previous standard while reducing bit rate by 40%. The chip was designed and fabricated in a 28-nm CMOS technology and used to build industry-leading 4K and 8K broadcasting systems.
Original language | English |
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Article number | 8388869 |
Pages (from-to) | 1930-1938 |
Number of pages | 9 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 26 |
Issue number | 10 |
DOIs | |
Publication status | Published - 2018 Oct |
Externally published | Yes |
Keywords
- Digital video broadcasting
- high-efficiency video coding (HEVC)
- motion estimation (ME)
- multichip configuration
- video codecs
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering