A single-chip 10Gb/s transceiver LSI using SiGe SOI/BiCMOS

S. Ueno, K. Watanabe, T. Kato, T. Shinohara, K. Mikami, T. Hashimoto, A. Takai, K. Washio, R. Takeyari, T. Harada

Research output: Contribution to journalConference articlepeer-review

16 Citations (Scopus)

Abstract

A single-chip transceiver large scale integration (LSI) was described with transmitter, receiver, data loop-back from receiver to transmitter at higher level of integration. The LSI comprised of PLL, control circuits, 16-channel input first in first out (FIFO), 16:1 mux, data input decision circuit, clock and data recovery (CDR) circuit, 1:16 demux, a generator. The transceiver LSI showed best characteristics for operating at low supply voltage with low power dissipation.

Original languageEnglish
Pages (from-to)82-83+435
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication statusPublished - 2001 Jan 1
Externally publishedYes
EventDigest of Technical Papers - IEEE International Solid-State Circuits Conference -
Duration: 2001 Feb 52001 Feb 6

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A single-chip 10Gb/s transceiver LSI using SiGe SOI/BiCMOS'. Together they form a unique fingerprint.

Cite this