A simulation methodology for single-electron multiple-valued logics and its application to a latched parallel counter

Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

This paper introduces a methodology for simulating single-electron-transistor (SET)-based multiple-valued logics (MVLs). First, a physics-based analytical model for SET is described, and then a procedure for extracting parameters from measured characteristics is explained. After that, simulated and experimental results for basic MVL circuits are compared. As an advanced example of SET-based logics, a latched parallel counter, which is one of the most important components in arithmetic circuits, is newly designed and analyzed by a simulation. It is found that a SET-based 7-3 counter can be constructed with less than 1/10 the number of devices needed for a conventional circuit and can operate at a moderate speed with 1/100 the conventional power consumption.

Original languageEnglish
Pages (from-to)1818-1826
Number of pages9
JournalIEICE Transactions on Electronics
VolumeE87-C
Issue number11
Publication statusPublished - 2004 Nov

Keywords

  • Analytical model
  • Counter
  • Multiple-valued logic (MVL)
  • SPICE
  • Single-electron transistor (SET)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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