A simplified distribution parasitic capacitance model for on-chip spiral inductors

Toru Masuda; Akihiro Kodama; Takahiro Nakamura; Nobuhiro Shiramizu; Shin Ichiro Wada; Takashi Hashimoto; Katsuyoshi Washio

doi:10.1109/SMIC.2005.1587920

A simplified distribution parasitic capacitance model for on-chip spiral inductors

Toru Masuda, Akihiro Kodama, Takahiro Nakamura, Nobuhiro Shiramizu, Shin Ichiro Wada, Takashi Hashimoto, Katsuyoshi Washio

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A modeling methodology for determining simply distributed parasitic capacitances used in a lumped equivalent circuit of silicon monolithic spiral inductors is proposed. To calculate the capacitances for the obtained model, the degeneration factors for the total amount of distributed parasitic-capacitances are introduced. A Q-factor modeling-error of less than 9.4% was obtained by comparing the measured and modeled characteristics in the microwave region.

Original language	English
Title of host publication	2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers
Pages	111-114
Number of pages	4
DOIs	https://doi.org/10.1109/SMIC.2005.1587920
Publication status	Published - 2006 Dec 1
Externally published	Yes
Event	2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - San Diego, CA, United States Duration: 2006 Jan 18 → 2006 Jan 20

Publication series

Name	2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers
Volume	2006

Other

Other	2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems
Country/Territory	United States
City	San Diego, CA
Period	06/1/18 → 06/1/20

Keywords

Equivalent circuit model
Parasitic capacitance
Silicon substrate
Spiral inductor

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/SMIC.2005.1587920

Cite this

Masuda, T., Kodama, A., Nakamura, T., Shiramizu, N., Wada, S. I., Hashimoto, T., & Washio, K. (2006). A simplified distribution parasitic capacitance model for on-chip spiral inductors. In 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers (pp. 111-114). [1587920] (2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers; Vol. 2006). https://doi.org/10.1109/SMIC.2005.1587920

A simplified distribution parasitic capacitance model for on-chip spiral inductors. / Masuda, Toru; Kodama, Akihiro; Nakamura, Takahiro et al.

2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers. 2006. p. 111-114 1587920 (2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Masuda, T, Kodama, A, Nakamura, T, Shiramizu, N, Wada, SI, Hashimoto, T & Washio, K 2006, A simplified distribution parasitic capacitance model for on-chip spiral inductors. in 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers., 1587920, 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers, vol. 2006, pp. 111-114, 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, San Diego, CA, United States, 06/1/18. https://doi.org/10.1109/SMIC.2005.1587920

Masuda T, Kodama A, Nakamura T, Shiramizu N, Wada SI, Hashimoto T et al. A simplified distribution parasitic capacitance model for on-chip spiral inductors. In 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers. 2006. p. 111-114. 1587920. (2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers). https://doi.org/10.1109/SMIC.2005.1587920

@inproceedings{547ff0fac5914a0a923956e8fa0314e7,

title = "A simplified distribution parasitic capacitance model for on-chip spiral inductors",

abstract = "A modeling methodology for determining simply distributed parasitic capacitances used in a lumped equivalent circuit of silicon monolithic spiral inductors is proposed. To calculate the capacitances for the obtained model, the degeneration factors for the total amount of distributed parasitic-capacitances are introduced. A Q-factor modeling-error of less than 9.4% was obtained by comparing the measured and modeled characteristics in the microwave region.",

keywords = "Equivalent circuit model, Parasitic capacitance, Silicon substrate, Spiral inductor",

author = "Toru Masuda and Akihiro Kodama and Takahiro Nakamura and Nobuhiro Shiramizu and Wada, {Shin Ichiro} and Takashi Hashimoto and Katsuyoshi Washio",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/SMIC.2005.1587920",

language = "English",

isbn = "0780394720",

series = "2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers",

pages = "111--114",

booktitle = "2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers",

note = "2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems ; Conference date: 18-01-2006 Through 20-01-2006",

}

TY - GEN

T1 - A simplified distribution parasitic capacitance model for on-chip spiral inductors

AU - Masuda, Toru

AU - Kodama, Akihiro

AU - Nakamura, Takahiro

AU - Shiramizu, Nobuhiro

AU - Wada, Shin Ichiro

AU - Hashimoto, Takashi

AU - Washio, Katsuyoshi

PY - 2006/12/1

Y1 - 2006/12/1

N2 - A modeling methodology for determining simply distributed parasitic capacitances used in a lumped equivalent circuit of silicon monolithic spiral inductors is proposed. To calculate the capacitances for the obtained model, the degeneration factors for the total amount of distributed parasitic-capacitances are introduced. A Q-factor modeling-error of less than 9.4% was obtained by comparing the measured and modeled characteristics in the microwave region.

AB - A modeling methodology for determining simply distributed parasitic capacitances used in a lumped equivalent circuit of silicon monolithic spiral inductors is proposed. To calculate the capacitances for the obtained model, the degeneration factors for the total amount of distributed parasitic-capacitances are introduced. A Q-factor modeling-error of less than 9.4% was obtained by comparing the measured and modeled characteristics in the microwave region.

KW - Equivalent circuit model

KW - Parasitic capacitance

KW - Silicon substrate

KW - Spiral inductor

UR - http://www.scopus.com/inward/record.url?scp=33847032554&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33847032554&partnerID=8YFLogxK

U2 - 10.1109/SMIC.2005.1587920

DO - 10.1109/SMIC.2005.1587920

M3 - Conference contribution

AN - SCOPUS:33847032554

SN - 0780394720

SN - 9780780394728

T3 - 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers

SP - 111

EP - 114

BT - 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers

T2 - 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

Y2 - 18 January 2006 through 20 January 2006

ER -

A simplified distribution parasitic capacitance model for on-chip spiral inductors

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this