A simplified distribution parasitic capacitance model for on-chip spiral inductors

Toru Masuda; Akihiro Kodama; Takahiro Nakamura; Nobuhiro Shiramizu; Shin Ichiro Wada; Takashi Hashimoto; Katsuyoshi Washio

doi:10.1109/SMIC.2005.1587920

A simplified distribution parasitic capacitance model for on-chip spiral inductors

Toru Masuda, Akihiro Kodama, Takahiro Nakamura, Nobuhiro Shiramizu, Shin Ichiro Wada, Takashi Hashimoto, Katsuyoshi Washio

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A modeling methodology for determining simply distributed parasitic capacitances used in a lumped equivalent circuit of silicon monolithic spiral inductors is proposed. To calculate the capacitances for the obtained model, the degeneration factors for the total amount of distributed parasitic-capacitances are introduced. A Q-factor modeling-error of less than 9.4% was obtained by comparing the measured and modeled characteristics in the microwave region.

Original language	English
Title of host publication	2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers
Pages	111-114
Number of pages	4
DOIs	https://doi.org/10.1109/SMIC.2005.1587920
Publication status	Published - 2006 Dec 1
Externally published	Yes
Event	2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - San Diego, CA, United States Duration: 2006 Jan 18 → 2006 Jan 20

Publication series

Name	2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers
Volume	2006

Other

Other	2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems
Country	United States
City	San Diego, CA
Period	06/1/18 → 06/1/20

Keywords

Equivalent circuit model
Parasitic capacitance
Silicon substrate
Spiral inductor

ASJC Scopus subject areas

Engineering(all)

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10.1109/SMIC.2005.1587920

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Masuda, T., Kodama, A., Nakamura, T., Shiramizu, N., Wada, S. I., Hashimoto, T., & Washio, K. (2006). A simplified distribution parasitic capacitance model for on-chip spiral inductors. In 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers (pp. 111-114). [1587920] (2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers; Vol. 2006). https://doi.org/10.1109/SMIC.2005.1587920

A simplified distribution parasitic capacitance model for on-chip spiral inductors. / Masuda, Toru; Kodama, Akihiro; Nakamura, Takahiro; Shiramizu, Nobuhiro; Wada, Shin Ichiro; Hashimoto, Takashi; Washio, Katsuyoshi.

2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers. 2006. p. 111-114 1587920 (2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Masuda, T, Kodama, A, Nakamura, T, Shiramizu, N, Wada, SI, Hashimoto, T & Washio, K 2006, A simplified distribution parasitic capacitance model for on-chip spiral inductors. in 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers., 1587920, 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers, vol. 2006, pp. 111-114, 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, San Diego, CA, United States, 06/1/18. https://doi.org/10.1109/SMIC.2005.1587920

Masuda T, Kodama A, Nakamura T, Shiramizu N, Wada SI, Hashimoto T et al. A simplified distribution parasitic capacitance model for on-chip spiral inductors. In 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers. 2006. p. 111-114. 1587920. (2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers). https://doi.org/10.1109/SMIC.2005.1587920

Masuda, Toru ; Kodama, Akihiro ; Nakamura, Takahiro ; Shiramizu, Nobuhiro ; Wada, Shin Ichiro ; Hashimoto, Takashi ; Washio, Katsuyoshi. / A simplified distribution parasitic capacitance model for on-chip spiral inductors. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers. 2006. pp. 111-114 (2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers).

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abstract = "A modeling methodology for determining simply distributed parasitic capacitances used in a lumped equivalent circuit of silicon monolithic spiral inductors is proposed. To calculate the capacitances for the obtained model, the degeneration factors for the total amount of distributed parasitic-capacitances are introduced. A Q-factor modeling-error of less than 9.4% was obtained by comparing the measured and modeled characteristics in the microwave region.",

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AU - Washio, Katsuyoshi

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A simplified distribution parasitic capacitance model for on-chip spiral inductors

Abstract

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Keywords

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