A simplified distribution parasitic capacitance model for on-chip spiral inductors

Toru Masuda, Akihiro Kodama, Takahiro Nakamura, Nobuhiro Shiramizu, Shin Ichiro Wada, Takashi Hashimoto, Katsuyoshi Washio

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A modeling methodology for determining simply distributed parasitic capacitances used in a lumped equivalent circuit of silicon monolithic spiral inductors is proposed. To calculate the capacitances for the obtained model, the degeneration factors for the total amount of distributed parasitic-capacitances are introduced. A Q-factor modeling-error of less than 9.4% was obtained by comparing the measured and modeled characteristics in the microwave region.

Original languageEnglish
Title of host publication2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers
Pages111-114
Number of pages4
DOIs
Publication statusPublished - 2006 Dec 1
Externally publishedYes
Event2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - San Diego, CA, United States
Duration: 2006 Jan 182006 Jan 20

Publication series

Name2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers
Volume2006

Other

Other2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems
CountryUnited States
CitySan Diego, CA
Period06/1/1806/1/20

Keywords

  • Equivalent circuit model
  • Parasitic capacitance
  • Silicon substrate
  • Spiral inductor

ASJC Scopus subject areas

  • Engineering(all)

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