A shared cache for a chip multi vector processor

Akihiro Musa, Yoshiei Sato, Takashi Soga, Koki Okabe, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

This paper discusses the design of a chip multi vector processor (CMVP), especially examining the effects of an on-chip cache when the off-chip memory bandwidth is limited. As chip multiprocessors (CMPs) have become the mainstream in commodity scalar processors, the CMP architecture will be adopted to design of vector processors in the near future for harnessing a large number of transistors on a chip. To keep a higher sustained performance in execution of scientific and engineering applications, a vector processor (core) generally requires the ratio of the memory bandwidth to the arithmetic performance of at least 4 bytes/flop (B/FLOP). However, vector supercomputers have been encountering the memory wall problem due to the limited pin bandwidth. Therefore, we propose an on-chip shared cache to maintain the effective memory bandwidth for a CMVP. We evaluate the performance of the CMVP based on the NEC SX vector architecture using real scientific applications. Especially, we examine the caching effect on the sustained performance when the B/FLOP rate is decreased. The experimental results indicate that an 8 MB on-chip shared cache can improve the performance of a four-core CMVP by 15% to 40%, compared with that without the cache. This is because the shared cache can increase cache hit rates of multi-threads. Here, the shared cache employs a miss status handling registers, which has the potential for accelerating difference schemes in scientific and engineering applications. Moreover, we show that the 2 B/FLOP is enough for the CMVP to achieve a high scalability when the on-chip cache is employed.

Original languageEnglish
Title of host publicationProceedings of the 9th MEDEA Workshop on MEmory Performance
Subtitle of host publicationDEaling with Applications, Systems and Architecture, MEDEA '08, Held in Conjunction with the PACT 2008 Conference
Pages24-29
Number of pages6
Volume310
DOIs
Publication statusPublished - 2008 Dec 1
Event9th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '08, Held in Conjunction with the PACT 2008 Conference - Toronto, ON, Canada
Duration: 2008 Oct 262008 Oct 26

Other

Other9th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '08, Held in Conjunction with the PACT 2008 Conference
CountryCanada
CityToronto, ON
Period08/10/2608/10/26

Keywords

  • chip multiprocessor
  • memory system
  • performance characterization
  • scientific application
  • vector cache
  • vector processing

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Software
  • Hardware and Architecture

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