A scalable shield-bitline-overdrive technique for sub-1.5 v chain FeRAMs

Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shin Ichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Sumiko Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


A ferroelectric capacitor overdrive technique with shield-bitline drive has been demonstrated and verified by a 130 nm 576 Kb test chip with a 0.7191 μm2 cell. First, cell signal degradation and bitline-to-bitline coupling noise worsened by wide cell signal distribution in low voltage scaled FeRAMs are discussed. Next, the shield-bitline-overdrive technique is presented. This technique applies a 0.24 V higher bias to the ferroelectric capacitor through bitline-to-bitline coupling during the read operation without increasing device stress, and eliminates bitline-to-bitline coupling noise. The measured tail-to-tail cell signal is improved by 100 mV and effectively doubles for 1.3 V array operation. The area penalty of the proposed scheme is 0.9% of the 576 Kb cell array, and the access time penalty is 5 ns. The effect of this technique will be enhanced by cell shrink as the bitline-to-bitline coupling ratio increases. A tail-to-tail cell signal window of more than 200 mV is expected in 1.3 V 256 Mb and 1.2 V 512 Mb chain FeRAMs, whereas the tail-to-tail cell signal window without overdrive would degrade to 95 mV for 256 Mb and 60 mV for 512 Mb.

Original languageEnglish
Article number5954136
Pages (from-to)2171-2179
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Issue number9
Publication statusPublished - 2011 Sep


  • Chain FeRAM
  • FeRAM
  • ferroelectric memory
  • low voltage
  • signal

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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