A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM

Daisaburo Takashima; Hidehiro Shiga; Daisuke Hashimoto; Tadashi Miyakawa; Shinichiro Shiratake; Katsuhiko Hoya; Ryu Ogiwara; Ryosuke Takizawa; Sumiko Doumae; Ryo Fukuda; Yohji Watanabe; Shuso Fujii; Tohru Ozaki; Hiroyuki Kanaya; Susumu Shuto; Koji Yamakawa; Iwao Kunishima; Takeshi Hamamoto; Akihiro Nitayama

doi:10.1109/ISSCC.2010.5433950

A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM

Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Sumiko Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama

Center for Innovative Integrated Electronic Systems (CIES)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Citations (Scopus)

Abstract

A ferroelectric RAM, especially Chain FeRAM™ [1], can boost the performance of memory systems such as HDD and SSD. Chain FeRAM can be used as a non-volatile RAM cache in these memory systems, improving effective write bandwidth by minimizing the frequency of seeks to disk [2] and program/erase access to NAND flash memory [3]. A 128Mb Chain FeRAM with DDR2 interface has been previously developed [4]. However, the memory systems require further improvement to reach memory capacity of 256Mb while operating with a lower voltage of 1.3V to meet DDR3/LPDDR2 interface requirements and to accommodate device scaling. We demonstrate a ferroelectric capacitor overdrive technique with shield bitline drive. This technique applies a larger bias to the ferroelectric capacitor in a read operation, resulting in a larger readout cell signal in low-voltage operation.

Original language	English
Title of host publication	2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers
Pages	262-263
Number of pages	2
DOIs	https://doi.org/10.1109/ISSCC.2010.5433950
Publication status	Published - 2010 May 18
Event	2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, CA, United States Duration: 2010 Feb 7 → 2010 Feb 11

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	53
ISSN (Print)	0193-6530

Conference

Conference	2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
Country/Territory	United States
City	San Francisco, CA
Period	10/2/7 → 10/2/11

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2010.5433950

Cite this

Takashima, D., Shiga, H., Hashimoto, D., Miyakawa, T., Shiratake, S., Hoya, K., Ogiwara, R., Takizawa, R., Doumae, S., Fukuda, R., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Shuto, S., Yamakawa, K., Kunishima, I., Hamamoto, T., & Nitayama, A. (2010). A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM. In 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers (pp. 262-263). [5433950] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 53). https://doi.org/10.1109/ISSCC.2010.5433950

A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM. / Takashima, Daisaburo; Shiga, Hidehiro; Hashimoto, Daisuke et al.

2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. 2010. p. 262-263 5433950 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 53).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Takashima, D, Shiga, H, Hashimoto, D, Miyakawa, T, Shiratake, S, Hoya, K, Ogiwara, R, Takizawa, R, Doumae, S, Fukuda, R, Watanabe, Y, Fujii, S, Ozaki, T, Kanaya, H, Shuto, S, Yamakawa, K, Kunishima, I, Hamamoto, T & Nitayama, A 2010, A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM. in 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers., 5433950, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 53, pp. 262-263, 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010, San Francisco, CA, United States, 10/2/7. https://doi.org/10.1109/ISSCC.2010.5433950

Takashima D, Shiga H, Hashimoto D, Miyakawa T, Shiratake S, Hoya K et al. A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM. In 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. 2010. p. 262-263. 5433950. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2010.5433950

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A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM

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