A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM

Daisaburo Takashima; Hidehiro Shiga; Daisuke Hashimoto; Tadashi Miyakawa; Shinichiro Shiratake; Katsuhiko Hoya; Ryu Ogiwara; Ryosuke Takizawa; Sumiko Doumae; Ryo Fukuda; Yohji Watanabe; Shuso Fujii; Tohru Ozaki; Hiroyuki Kanaya; Susumu Shuto; Koji Yamakawa; Iwao Kunishima; Takeshi Hamamoto; Akihiro Nitayama

doi:10.1109/ISSCC.2010.5433950

A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM

Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Sumiko Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama

Center for Innovative Integrated Electronic Systems (CIES)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Citations (Scopus)

Abstract

A ferroelectric RAM, especially Chain FeRAM™ [1], can boost the performance of memory systems such as HDD and SSD. Chain FeRAM can be used as a non-volatile RAM cache in these memory systems, improving effective write bandwidth by minimizing the frequency of seeks to disk [2] and program/erase access to NAND flash memory [3]. A 128Mb Chain FeRAM with DDR2 interface has been previously developed [4]. However, the memory systems require further improvement to reach memory capacity of 256Mb while operating with a lower voltage of 1.3V to meet DDR3/LPDDR2 interface requirements and to accommodate device scaling. We demonstrate a ferroelectric capacitor overdrive technique with shield bitline drive. This technique applies a larger bias to the ferroelectric capacitor in a read operation, resulting in a larger readout cell signal in low-voltage operation.

Original language	English
Title of host publication	2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers
Pages	262-263
Number of pages	2
DOIs	https://doi.org/10.1109/ISSCC.2010.5433950
Publication status	Published - 2010 May 18
Event	2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, CA, United States Duration: 2010 Feb 7 → 2010 Feb 11

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	53
ISSN (Print)	0193-6530

Conference

Conference	2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
Country	United States
City	San Francisco, CA
Period	10/2/7 → 10/2/11

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2010.5433950

Fingerprint Dive into the research topics of 'A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM'. Together they form a unique fingerprint.

Cite this

Takashima, D., Shiga, H., Hashimoto, D., Miyakawa, T., Shiratake, S., Hoya, K., Ogiwara, R., Takizawa, R., Doumae, S., Fukuda, R., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Shuto, S., Yamakawa, K., Kunishima, I., Hamamoto, T., & Nitayama, A. (2010). A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM. In 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers (pp. 262-263). [5433950] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 53). https://doi.org/10.1109/ISSCC.2010.5433950

A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM. / Takashima, Daisaburo; Shiga, Hidehiro; Hashimoto, Daisuke; Miyakawa, Tadashi; Shiratake, Shinichiro; Hoya, Katsuhiko; Ogiwara, Ryu; Takizawa, Ryosuke; Doumae, Sumiko; Fukuda, Ryo; Watanabe, Yohji; Fujii, Shuso; Ozaki, Tohru; Kanaya, Hiroyuki; Shuto, Susumu; Yamakawa, Koji; Kunishima, Iwao; Hamamoto, Takeshi; Nitayama, Akihiro.

2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. 2010. p. 262-263 5433950 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 53).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Takashima, D, Shiga, H, Hashimoto, D, Miyakawa, T, Shiratake, S, Hoya, K, Ogiwara, R, Takizawa, R, Doumae, S, Fukuda, R, Watanabe, Y, Fujii, S, Ozaki, T, Kanaya, H, Shuto, S, Yamakawa, K, Kunishima, I, Hamamoto, T & Nitayama, A 2010, A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM. in 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers., 5433950, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 53, pp. 262-263, 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010, San Francisco, CA, United States, 10/2/7. https://doi.org/10.1109/ISSCC.2010.5433950

Takashima D, Shiga H, Hashimoto D, Miyakawa T, Shiratake S, Hoya K et al. A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM. In 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. 2010. p. 262-263. 5433950. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2010.5433950

Takashima, Daisaburo ; Shiga, Hidehiro ; Hashimoto, Daisuke ; Miyakawa, Tadashi ; Shiratake, Shinichiro ; Hoya, Katsuhiko ; Ogiwara, Ryu ; Takizawa, Ryosuke ; Doumae, Sumiko ; Fukuda, Ryo ; Watanabe, Yohji ; Fujii, Shuso ; Ozaki, Tohru ; Kanaya, Hiroyuki ; Shuto, Susumu ; Yamakawa, Koji ; Kunishima, Iwao ; Hamamoto, Takeshi ; Nitayama, Akihiro. / A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM. 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers. 2010. pp. 262-263 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

@inproceedings{485849d94466404d8be01bb3ac60c01d,

title = "A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM",

abstract = "A ferroelectric RAM, especially Chain FeRAM{\texttrademark} [1], can boost the performance of memory systems such as HDD and SSD. Chain FeRAM can be used as a non-volatile RAM cache in these memory systems, improving effective write bandwidth by minimizing the frequency of seeks to disk [2] and program/erase access to NAND flash memory [3]. A 128Mb Chain FeRAM with DDR2 interface has been previously developed [4]. However, the memory systems require further improvement to reach memory capacity of 256Mb while operating with a lower voltage of 1.3V to meet DDR3/LPDDR2 interface requirements and to accommodate device scaling. We demonstrate a ferroelectric capacitor overdrive technique with shield bitline drive. This technique applies a larger bias to the ferroelectric capacitor in a read operation, resulting in a larger readout cell signal in low-voltage operation.",

author = "Daisaburo Takashima and Hidehiro Shiga and Daisuke Hashimoto and Tadashi Miyakawa and Shinichiro Shiratake and Katsuhiko Hoya and Ryu Ogiwara and Ryosuke Takizawa and Sumiko Doumae and Ryo Fukuda and Yohji Watanabe and Shuso Fujii and Tohru Ozaki and Hiroyuki Kanaya and Susumu Shuto and Koji Yamakawa and Iwao Kunishima and Takeshi Hamamoto and Akihiro Nitayama",

year = "2010",

month = may,

day = "18",

doi = "10.1109/ISSCC.2010.5433950",

language = "English",

isbn = "9781424460342",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

pages = "262--263",

booktitle = "2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers",

note = "2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 ; Conference date: 07-02-2010 Through 11-02-2010",

}

TY - GEN

T1 - A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM

AU - Takashima, Daisaburo

AU - Shiga, Hidehiro

AU - Hashimoto, Daisuke

AU - Miyakawa, Tadashi

AU - Shiratake, Shinichiro

AU - Hoya, Katsuhiko

AU - Ogiwara, Ryu

AU - Takizawa, Ryosuke

AU - Doumae, Sumiko

AU - Fukuda, Ryo

AU - Watanabe, Yohji

AU - Fujii, Shuso

AU - Ozaki, Tohru

AU - Kanaya, Hiroyuki

AU - Shuto, Susumu

AU - Yamakawa, Koji

AU - Kunishima, Iwao

AU - Hamamoto, Takeshi

AU - Nitayama, Akihiro

PY - 2010/5/18

Y1 - 2010/5/18

N2 - A ferroelectric RAM, especially Chain FeRAM™ [1], can boost the performance of memory systems such as HDD and SSD. Chain FeRAM can be used as a non-volatile RAM cache in these memory systems, improving effective write bandwidth by minimizing the frequency of seeks to disk [2] and program/erase access to NAND flash memory [3]. A 128Mb Chain FeRAM with DDR2 interface has been previously developed [4]. However, the memory systems require further improvement to reach memory capacity of 256Mb while operating with a lower voltage of 1.3V to meet DDR3/LPDDR2 interface requirements and to accommodate device scaling. We demonstrate a ferroelectric capacitor overdrive technique with shield bitline drive. This technique applies a larger bias to the ferroelectric capacitor in a read operation, resulting in a larger readout cell signal in low-voltage operation.

AB - A ferroelectric RAM, especially Chain FeRAM™ [1], can boost the performance of memory systems such as HDD and SSD. Chain FeRAM can be used as a non-volatile RAM cache in these memory systems, improving effective write bandwidth by minimizing the frequency of seeks to disk [2] and program/erase access to NAND flash memory [3]. A 128Mb Chain FeRAM with DDR2 interface has been previously developed [4]. However, the memory systems require further improvement to reach memory capacity of 256Mb while operating with a lower voltage of 1.3V to meet DDR3/LPDDR2 interface requirements and to accommodate device scaling. We demonstrate a ferroelectric capacitor overdrive technique with shield bitline drive. This technique applies a larger bias to the ferroelectric capacitor in a read operation, resulting in a larger readout cell signal in low-voltage operation.

UR - http://www.scopus.com/inward/record.url?scp=77952128336&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77952128336&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.2010.5433950

DO - 10.1109/ISSCC.2010.5433950

M3 - Conference contribution

AN - SCOPUS:77952128336

SN - 9781424460342

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 262

EP - 263

BT - 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers

T2 - 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010

Y2 - 7 February 2010 through 11 February 2010

ER -