TY - GEN
T1 - A scalable shield-bitline-overdrive technique for 1.3V chain FeRAM
AU - Takashima, Daisaburo
AU - Shiga, Hidehiro
AU - Hashimoto, Daisuke
AU - Miyakawa, Tadashi
AU - Shiratake, Shinichiro
AU - Hoya, Katsuhiko
AU - Ogiwara, Ryu
AU - Takizawa, Ryosuke
AU - Doumae, Sumiko
AU - Fukuda, Ryo
AU - Watanabe, Yohji
AU - Fujii, Shuso
AU - Ozaki, Tohru
AU - Kanaya, Hiroyuki
AU - Shuto, Susumu
AU - Yamakawa, Koji
AU - Kunishima, Iwao
AU - Hamamoto, Takeshi
AU - Nitayama, Akihiro
PY - 2010/5/18
Y1 - 2010/5/18
N2 - A ferroelectric RAM, especially Chain FeRAM™ [1], can boost the performance of memory systems such as HDD and SSD. Chain FeRAM can be used as a non-volatile RAM cache in these memory systems, improving effective write bandwidth by minimizing the frequency of seeks to disk [2] and program/erase access to NAND flash memory [3]. A 128Mb Chain FeRAM with DDR2 interface has been previously developed [4]. However, the memory systems require further improvement to reach memory capacity of 256Mb while operating with a lower voltage of 1.3V to meet DDR3/LPDDR2 interface requirements and to accommodate device scaling. We demonstrate a ferroelectric capacitor overdrive technique with shield bitline drive. This technique applies a larger bias to the ferroelectric capacitor in a read operation, resulting in a larger readout cell signal in low-voltage operation.
AB - A ferroelectric RAM, especially Chain FeRAM™ [1], can boost the performance of memory systems such as HDD and SSD. Chain FeRAM can be used as a non-volatile RAM cache in these memory systems, improving effective write bandwidth by minimizing the frequency of seeks to disk [2] and program/erase access to NAND flash memory [3]. A 128Mb Chain FeRAM with DDR2 interface has been previously developed [4]. However, the memory systems require further improvement to reach memory capacity of 256Mb while operating with a lower voltage of 1.3V to meet DDR3/LPDDR2 interface requirements and to accommodate device scaling. We demonstrate a ferroelectric capacitor overdrive technique with shield bitline drive. This technique applies a larger bias to the ferroelectric capacitor in a read operation, resulting in a larger readout cell signal in low-voltage operation.
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U2 - 10.1109/ISSCC.2010.5433950
DO - 10.1109/ISSCC.2010.5433950
M3 - Conference contribution
AN - SCOPUS:77952128336
SN - 9781424460342
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 262
EP - 263
BT - 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - Digest of Technical Papers
T2 - 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
Y2 - 7 February 2010 through 11 February 2010
ER -