A resilient 3-D stacked multicore processor fabricated using die-level 3-D integration and backside TSV technologies

K. W. Lee, H. Hashimoto, M. Onishi, Y. Sato, M. Murugesan, J. C. Bea, T. Fukushima, T. Tanaka, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

A highly dependable 3-D stacked multicore processor with TSV self-test and self-repair functions for highly area-efficient TSV repair has been proposed. The prototype 3-D stacked multicore processor with two layer structure is implemented using die-level 3-D integration and backside Cu TSV technologies. The basic functions of tier boundary scan and self-repair circuits via TSVs between each layer in the 3-D stacked multicore processor are successfully evaluated. X-ray computed tomography (X-ray CT) scanning technology is proposed as a nondestructive failure analysis method to characterize high-density TSVs integration, and bump joining qualities in the 3-D stacked multicore processor.

Original languageEnglish
Title of host publicationProceedings - Electronic Components and Technology Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages304-308
Number of pages5
ISBN (Electronic)9781479924073
DOIs
Publication statusPublished - 2014 Sep 11
Event64th Electronic Components and Technology Conference, ECTC 2014 - Orlando, United States
Duration: 2014 May 272014 May 30

Publication series

NameProceedings - Electronic Components and Technology Conference
ISSN (Print)0569-5503

Other

Other64th Electronic Components and Technology Conference, ECTC 2014
CountryUnited States
CityOrlando
Period14/5/2714/5/30

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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