A preliminary chip evaluation toward over 50Mfps burst global shutter stacked CMOS image sensor

Manabu Suzuki, Masashi Suzuki, Rihito Kuroda, Shigetoshi Sugawa

Research output: Contribution to journalConference articlepeer-review

3 Citations (Scopus)

Abstract

A preliminary chip evaluation targeting a development of over 50Mfps burst global shutter stacked CMOS image sensor is reported in this work. A two dimensional CMOS image sensor chip with 34.56μmH × 34.56μmV equivalent pitch 25H × 100V pixels with ultrahigh speed charge collection capability and in-pixel 80 analog memories was designed and fabricated using a 0.18μm 1-Poly-Si 5- Metal layer CMOS image sensor technology. The operation of the fabricated chip was confirmed to work with two modes: in-pixel correlated double sampling (CDS) mode with 80 frames up to 50 Mfps and direct readout mode with 40 frames up to 71.4 Mfps. Based on the developed architecture, over 50 Mfps with about 400 consecutive frames with 100% fill factor will be achieved using backside illumination 3D stacking technology with high-density analog memory.

Original languageEnglish
Pages (from-to)3981-3984
Number of pages4
JournalIS and T International Symposium on Electronic Imaging Science and Technology
DOIs
Publication statusPublished - 2018
EventImage Sensors and Imaging Systems 2018, IMSE 2018 - Burlingame, United States
Duration: 2018 Jan 282018 Feb 1

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications
  • Human-Computer Interaction
  • Software
  • Electrical and Electronic Engineering
  • Atomic and Molecular Physics, and Optics

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