A power-down circuit scheme using data-preserving complementary pass transistor flip-flop for low-power high-performance multi-threshold CMOS LSI

Ki Tae Park, Tomokatsu Mizukusa, Hyo Sig Won, Kyu Myung Choi, Jeong Taek Kong, Hiroyuki Kurino, Mitsumasa Koyanagi

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Engineering & Materials Science

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