A power-down circuit scheme using data-preserving complementary pass transistor flip-flop for low-power high-performance multi-threshold CMOS LSI

Ki Tae Park, Tomokatsu Mizukusa, Hyo Sig Won, Kyu Myung Choi, Jeong Taek Kong, Hiroyuki Kurino, Mitsumasa Koyanagi

Research output: Contribution to journalArticlepeer-review

Abstract

A new power-down circuit scheme using data-preserving complementary pass transistor flip-flop circuit for low-power, high-performance Multi-Threshold voltage CMOS (MTCMOS) LSI is presented. The proposed circuit can preserve a stored data during power-down period while maintaining low leakage current without any extra circuit and complex timing design. The flip-flop provides 24% improved delay and 30% less silicon area compared to conventional MTCMOS flip-flop circuit. A 16-bits DSP processor core using the proposed circuit and 0.18 μm CMOS technology was designed. The DSP chip was successfully operated at 120 MHz, 1.65 V and its total leakage current in power-down mode was four orders smaller than conventional DSP chip.

Original languageEnglish
Pages (from-to)645-648
Number of pages4
JournalIEICE Transactions on Electronics
VolumeE87-C
Issue number4
Publication statusPublished - 2004 Apr

Keywords

  • Complementary pass transistor
  • Data-preserving
  • Low-power
  • MTCMOS
  • Power-down circuit scheme

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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