This paper describes a picosecond-accuracy digital vernier-based single-chip time interval counter (TIC) LSI applicable to timing calibration in state-of-the-art high-speed LSI test systems. Jitter performance is improved to three times higher than in conventional circuitry by using a new skew detection circuit that is insensitive to the jitter caused by metastable transitions in flip-flops. All the hardware except the signal sources has been integrated on a Si bipolar 2.5K-gate array LSI by developing fully digitally processed beat-signal and trigger control circuits. The chip is mounted on a dedicated ceramic package employing coplanar lines with a 3-GHz bandwidth. Overall performance achieves 2.3-ps standard deviation, ±3-ps linearity, zero-skew offset of ±2.7 ps, and an equivalent input slew time of 33.6 ps/V at input clock rates up to 700 MHz.
ASJC Scopus subject areas
- Electrical and Electronic Engineering