A personal-use single-chip emulation system using a dynamically reconfigurable logic array named Flexible Processor II (FP2) has been developed. It can emulate large target circuit by sequential execution of sub-circuits divided from the target circuit. The size of the target circuit for emulation is theoretically unlimited. In order to realize such features, FP2 is equipped with Temporal Communication Module (TCM) and Flexible Logic Element (FLE), which are essential for handling temporal data communication between divided sub-circuits and for reducing the amount of configuration data, respectively. A place-and-route tool for FP2 named PELOC, which takes care of sequential execution of divided sub-circuits and carries out the temporal partitioning, spatial partitioning, placement, routing and configuration data generation has also been developed. We have developed a single-chip emulation system on a printed circuit board and confirmed that its emulation speed is several hundred times faster than that of verilog simulator and in some cases also faster than a conventional emulator using lots of parallel-connected FPGAs.