A parallel architecture for recursive least square method

Koichi Hashimoto, Hidenori Kimura

Research output: Contribution to journalArticle

Abstract

Recent developments in computer technology have enabled the real‐time treatment of signal processing with a large amount of computation which had been considered to be impossible. Moreover, with the development of LSI technology, it has become possible to speed up the execution of the algorithms by parallel computing hardware. This paper discusses a parallel architecture for the recursive least square method of system identification fitted for VLSI. If n is the order of system to be identified, the complexity T(n) required for updating the estimate at each measurement is Ts(n) = o(n2), using a single serial processor. However, it can be reduced to Tp(n) = o(n) by using the architecture consisting of (2n + 6) elementary processors and a set of delay units. Moreover, we discuss a method to speed up p‐time updates from Ts(n, p) = o(n2p) to TM(n, p) = o(n + p) using o(np) elementary processors by vectorizing the measurements.

Original languageEnglish
Pages (from-to)1-11
Number of pages11
JournalElectronics and Communications in Japan (Part I: Communications)
Volume70
Issue number4
DOIs
Publication statusPublished - 1987 Jan 1
Externally publishedYes

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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