A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor

M. Sekikawa, K. Kiyoyama, H. Hasegawa, K. Miura, T. Fukushima, S. Ikeda, T. Tanaka, H. Ohno, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

A novel reconfigurable logic block with SPRAM (SPin-transfer torque RAM) is demonstrated. Magnetic elements of 50 × 200 nm 2 in area and CMOS logic are fully integrated. Laboratory experimental results show that our reconfigurable logic block achieves 25 MHz read out operation with the magnetic resistance of 1.62 kω (parallel) and the MR ratio is 91.7 %.

Original languageEnglish
Title of host publication2008 IEEE International Electron Devices Meeting, IEDM 2008
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 IEEE International Electron Devices Meeting, IEDM 2008 - San Francisco, CA, United States
Duration: 2008 Dec 152008 Dec 17

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Other

Other2008 IEEE International Electron Devices Meeting, IEDM 2008
Country/TerritoryUnited States
CitySan Francisco, CA
Period08/12/1508/12/17

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Fingerprint

Dive into the research topics of 'A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor'. Together they form a unique fingerprint.

Cite this