A Novel High-Speed Latching Operation Flip-Flop (HLO-FF) Circuit and its Application to a 19-Gb/s Decision Circuit Using a 0.2-μm GaAs MESFET

Koichi Murata; Taiichi Otsuji; Eiichi Sano; Masanobu Ohhata; Masao Suzuki; Minoru Togashi

doi:10.1109/4.466072

A Novel High-Speed Latching Operation Flip-Flop (HLO-FF) Circuit and its Application to a 19-Gb/s Decision Circuit Using a 0.2-μm GaAs MESFET

Koichi Murata, Taiichi Otsuji, Eiichi Sano, Masanobu Ohhata, Masao Suzuki, Minoru Togashi

Research output: Contribution to journal › Article › peer-review

34 Citations (Scopus)

Abstract

This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs Low-power Source-Coupled FET Logic (LSCFL). We reveal the high-speed operation mechanism of the HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series-gated master slave flip-flops and HLO-FF's based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision IC's confirm the accuracy of our analytical method and the high-speed operation of a HLO-FF decision circuit at 19 Gb/s.

Original language	English
Pages (from-to)	1101-1108
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	30
Issue number	10
DOIs	https://doi.org/10.1109/4.466072
Publication status	Published - 1995 Oct
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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@article{ad991a2548f7462d97ba5524454ea0eb,

title = "A Novel High-Speed Latching Operation Flip-Flop (HLO-FF) Circuit and its Application to a 19-Gb/s Decision Circuit Using a 0.2-μm GaAs MESFET",

abstract = "This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs Low-power Source-Coupled FET Logic (LSCFL). We reveal the high-speed operation mechanism of the HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series-gated master slave flip-flops and HLO-FF's based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision IC's confirm the accuracy of our analytical method and the high-speed operation of a HLO-FF decision circuit at 19 Gb/s.",

author = "Koichi Murata and Taiichi Otsuji and Eiichi Sano and Masanobu Ohhata and Masao Suzuki and Minoru Togashi",

year = "1995",

month = oct,

doi = "10.1109/4.466072",

language = "English",

volume = "30",

pages = "1101--1108",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "10",

}

TY - JOUR

T1 - A Novel High-Speed Latching Operation Flip-Flop (HLO-FF) Circuit and its Application to a 19-Gb/s Decision Circuit Using a 0.2-μm GaAs MESFET

AU - Murata, Koichi

AU - Otsuji, Taiichi

AU - Sano, Eiichi

AU - Ohhata, Masanobu

AU - Suzuki, Masao

AU - Togashi, Minoru

PY - 1995/10

Y1 - 1995/10

N2 - This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs Low-power Source-Coupled FET Logic (LSCFL). We reveal the high-speed operation mechanism of the HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series-gated master slave flip-flops and HLO-FF's based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision IC's confirm the accuracy of our analytical method and the high-speed operation of a HLO-FF decision circuit at 19 Gb/s.

AB - This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs Low-power Source-Coupled FET Logic (LSCFL). We reveal the high-speed operation mechanism of the HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series-gated master slave flip-flops and HLO-FF's based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision IC's confirm the accuracy of our analytical method and the high-speed operation of a HLO-FF decision circuit at 19 Gb/s.

UR - http://www.scopus.com/inward/record.url?scp=0000342482&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0000342482&partnerID=8YFLogxK

U2 - 10.1109/4.466072

DO - 10.1109/4.466072

M3 - Article

AN - SCOPUS:0000342482

VL - 30

SP - 1101

EP - 1108

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 10

ER -

A Novel High-Speed Latching Operation Flip-Flop (HLO-FF) Circuit and its Application to a 19-Gb/s Decision Circuit Using a 0.2-μm GaAs MESFET

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