A Novel High-Speed Latching Operation Flip-Flop (HLO-FF) Circuit and its Application to a 19-Gb/s Decision Circuit Using a 0.2-μm GaAs MESFET

Koichi Murata, Taiichi Otsuji, Eiichi Sano, Masanobu Ohhata, Masao Suzuki, Minoru Togashi

Research output: Contribution to journalArticlepeer-review

30 Citations (Scopus)

Abstract

This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs Low-power Source-Coupled FET Logic (LSCFL). We reveal the high-speed operation mechanism of the HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series-gated master slave flip-flops and HLO-FF's based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision IC's confirm the accuracy of our analytical method and the high-speed operation of a HLO-FF decision circuit at 19 Gb/s.

Original languageEnglish
Pages (from-to)1101-1108
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume30
Issue number10
DOIs
Publication statusPublished - 1995 Jan 1
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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