A novel design of an FIR filter with a hierachical structure and its LSI implementation

Shogo Nakamura, Akiyoshi Kawahashi, Yoshihiko Horio, Makoto Kotani, Yukio Kadowaki

Research output: Contribution to journalArticle

Abstract

This paper describes a novel design of a linear‐phase FIR filter and its hardware. The proposed filter has a hierarchical building block structure of tapped‐cascaded lower‐order subfilters. Since this architecture can reduce the sensitivity of the rounded filter coefficients, an effective high‐speed processing of the subfilter can be performed by using adders instead of multipliers. Also, identical subfilters are arranged regularly so that the architecture is suitable for LSI implementation. Another important feature is that the design of the higher‐order FIR filter can be replaced with that of the lower‐order subfilter. An LSI implementation of about a 45‐order FIR filter also is described.

Original languageEnglish
Pages (from-to)69-77
Number of pages9
JournalElectronics and Communications in Japan (Part III: Fundamental Electronic Science)
Volume74
Issue number10
DOIs
Publication statusPublished - 1991
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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