TY - GEN
T1 - A novel chemically, thermally and electrically robust Cu interconnect structure with an organic non-porous ultralow-k dielectric fluorocarbon (k=2.2)
AU - Gu, X.
AU - Teramoto, A.
AU - Kuroda, R.
AU - Tomita, Y.
AU - Nemoto, T.
AU - Kuroki, S.
AU - Sugawa, S.
AU - Ohmi, T.
PY - 2012
Y1 - 2012
N2 - A novel chemically, thermally and electrically robust Cu damascene interconnects with an organic non-porous ultralow-k (ULK) dielectric fluorocarbon (k=2.2), deposited by an advanced microwave excited plasma enhanced CVD, is demonstrated. A practical nitrogen plasma treatment (NPT) was employed to minimize chemically damage introduction to fluorocarbon in post-etching cleaning and CMP processes. Also, a new structure with a delamination- protective-liner (DPL), instead of barrier-metal, between Cu and fluorocarbon is introduced to avoid thermally induced electrical degradation and to reduce the interconnect delay significantly (by >30% in 32 nm-node). Non-porous ULK fluorocarbon with NPT and DPL technologies is a promising candidate for high performance Cu interconnects.
AB - A novel chemically, thermally and electrically robust Cu damascene interconnects with an organic non-porous ultralow-k (ULK) dielectric fluorocarbon (k=2.2), deposited by an advanced microwave excited plasma enhanced CVD, is demonstrated. A practical nitrogen plasma treatment (NPT) was employed to minimize chemically damage introduction to fluorocarbon in post-etching cleaning and CMP processes. Also, a new structure with a delamination- protective-liner (DPL), instead of barrier-metal, between Cu and fluorocarbon is introduced to avoid thermally induced electrical degradation and to reduce the interconnect delay significantly (by >30% in 32 nm-node). Non-porous ULK fluorocarbon with NPT and DPL technologies is a promising candidate for high performance Cu interconnects.
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U2 - 10.1109/VLSIT.2012.6242490
DO - 10.1109/VLSIT.2012.6242490
M3 - Conference contribution
AN - SCOPUS:84866558714
SN - 9781467308458
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 119
EP - 120
BT - 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers
T2 - 2012 Symposium on VLSI Technology, VLSIT 2012
Y2 - 12 June 2012 through 14 June 2012
ER -