TY - GEN
T1 - A novel 3-d vertical FG NAND flash memory cell arrays using the separated sidewall control gate (S-SCG) for highly reliable MLC operation
AU - Seo, Moon Sik
AU - Lee, Bong Hoon
AU - Park, Sung Kye
AU - Endoh, Tetsuo
PY - 2011
Y1 - 2011
N2 - We propose a novel 3-dimensional (3-D) vertical floating gate (FG) type NAND flash memory cell arrays using the Separated - Sidewall Control Gate (S-SCG). This novel cell consists of one cylindrical FG with a line type control gate (CG) and S-SCG structure. For simplifying the process flow, we realized the common S-SCG lines by using the pre-stacked poly silicon layer, through which variable medium voltages are applied not only to control the electrically inverted S/D region but also to assist the program and erase operation. We successfully demonstrate the normal flash cell operation and show its superior performances in comparison with the conventional 3-D NAND cells by using the cylindrical 3-D device simulation. It is shown that the proposed cell can realize the highest CG coupling ratio, low voltage cell operation of program with 15V at Vth=4V and erase with 7V at Vth=-2V and good on/off read current margin by an order of over 1.5. Moreover, the proposed S-SCG cell array can fully suppress both the interference effects and the disturbance problems at the same time by removing the direct coupling effect in the same cell string, which are the most critical problems of the recent 3-D vertical stacked cell structures. Above all, the proposed cell array has good potential for Terabit 3-D vertical NAND flash cell array with highly reliable multi level cell (MLC) operation.
AB - We propose a novel 3-dimensional (3-D) vertical floating gate (FG) type NAND flash memory cell arrays using the Separated - Sidewall Control Gate (S-SCG). This novel cell consists of one cylindrical FG with a line type control gate (CG) and S-SCG structure. For simplifying the process flow, we realized the common S-SCG lines by using the pre-stacked poly silicon layer, through which variable medium voltages are applied not only to control the electrically inverted S/D region but also to assist the program and erase operation. We successfully demonstrate the normal flash cell operation and show its superior performances in comparison with the conventional 3-D NAND cells by using the cylindrical 3-D device simulation. It is shown that the proposed cell can realize the highest CG coupling ratio, low voltage cell operation of program with 15V at Vth=4V and erase with 7V at Vth=-2V and good on/off read current margin by an order of over 1.5. Moreover, the proposed S-SCG cell array can fully suppress both the interference effects and the disturbance problems at the same time by removing the direct coupling effect in the same cell string, which are the most critical problems of the recent 3-D vertical stacked cell structures. Above all, the proposed cell array has good potential for Terabit 3-D vertical NAND flash cell array with highly reliable multi level cell (MLC) operation.
KW - 3-D Vertical Stackde Cell
KW - Cylindrical FG
KW - Floating Gate
KW - GAA
KW - NAND flash memory
KW - S-SCG
KW - Sidewall Control Gate
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UR - http://www.scopus.com/inward/citedby.url?scp=79960011737&partnerID=8YFLogxK
U2 - 10.1109/IMW.2011.5873208
DO - 10.1109/IMW.2011.5873208
M3 - Conference contribution
AN - SCOPUS:79960011737
SN - 9781457702266
T3 - 2011 3rd IEEE International Memory Workshop, IMW 2011
BT - 2011 3rd IEEE International Memory Workshop, IMW 2011
T2 - 2011 3rd IEEE International Memory Workshop, IMW 2011
Y2 - 22 May 2011 through 25 May 2011
ER -