A normally-off GaN FET with high threshold voltage uniformity using a novel piezo neutralization technique

K. Ota, K. Endo, Y. Okamoto, Y. Ando, H. Miyamoto, H. Shimawaki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

50 Citations (Scopus)

Abstract

In this paper, we successfully demonstrate a recessed gate normally-off GaN FET on a silicon substrate with high threshold voltage (Vth) uniformity and low on-resistance. In order to realize high Vth uniformity, a novel Vth control technique is proposed, which we call "piezo neutralization technique". This technique includes a piezo neutralization (PNT) layer formed at the bottom of the gate recess. Since the PNT layer neutralizes the polarization charges under the gate, the V th comes to be independent of the gate-to-channel span. The fabricated normally-off GaN FET with PNT structure exhibits an excellent V th uniformity (σ(Vth)=18 mV) and a state-of-the-art combination of the specific on-resistance (RonA=500 mΩmm 2) and the breakdown voltage (VB>1000 V). The normally-off GaN FETs wtih PNT structure show great promise as power devices.

Original languageEnglish
Title of host publication2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest
Pages7.3.1-7.3.4
DOIs
Publication statusPublished - 2009 Dec 1
Externally publishedYes
Event2009 International Electron Devices Meeting, IEDM 2009 - Baltimore, MD, United States
Duration: 2009 Dec 72009 Dec 9

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Other

Other2009 International Electron Devices Meeting, IEDM 2009
CountryUnited States
CityBaltimore, MD
Period09/12/709/12/9

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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