In this paper, we successfully demonstrate a recessed gate normally-off GaN FET on a silicon substrate with high threshold voltage (Vth) uniformity and low on-resistance. In order to realize high Vth uniformity, a novel Vth control technique is proposed, which we call "piezo neutralization technique". This technique includes a piezo neutralization (PNT) layer formed at the bottom of the gate recess. Since the PNT layer neutralizes the polarization charges under the gate, the V th comes to be independent of the gate-to-channel span. The fabricated normally-off GaN FET with PNT structure exhibits an excellent V th uniformity (σ(Vth)=18 mV) and a state-of-the-art combination of the specific on-resistance (RonA=500 mΩmm 2) and the breakdown voltage (VB>1000 V). The normally-off GaN FETs wtih PNT structure show great promise as power devices.