A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAM

T. Kikuchi; S. Moriya; Y. Nakatsuka; H. Matsuoka; K. Nakazato; A. Nishida; H. Chakihara; M. Matsuoka; M. Moniwa

A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAM

T. Kikuchi, S. Moriya, Y. Nakatsuka, H. Matsuoka, K. Nakazato, A. Nishida, H. Chakihara, M. Matsuoka, M. Moniwa

Research output: Contribution to journal › Conference article › peer-review

Abstract

A New Vertically Stacked Poly-Si MOSFET has been studied as a novel technique that enables device integration without applying advanced node process. Reduced cell area size of 1.21μm² has been achieved in 6T-SRAM which is 60% of 130nm node based planer type cell. Operation speed of 533MHz was also confirmed.

Original language	English
Pages (from-to)	923-926
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting, IEDM
Publication status	Published - 2004
Externally published	Yes
Event	IEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States Duration: 2004 Dec 13 → 2004 Dec 15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

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title = "A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAM",

abstract = "A New Vertically Stacked Poly-Si MOSFET has been studied as a novel technique that enables device integration without applying advanced node process. Reduced cell area size of 1.21μm2 has been achieved in 6T-SRAM which is 60% of 130nm node based planer type cell. Operation speed of 533MHz was also confirmed.",

author = "T. Kikuchi and S. Moriya and Y. Nakatsuka and H. Matsuoka and K. Nakazato and A. Nishida and H. Chakihara and M. Matsuoka and M. Moniwa",

year = "2004",

language = "English",

pages = "923--926",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Electron Devices Meeting, 2004 IEDM ; Conference date: 13-12-2004 Through 15-12-2004",

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TY - JOUR

T1 - A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAM

AU - Kikuchi, T.

AU - Moriya, S.

AU - Nakatsuka, Y.

AU - Matsuoka, H.

AU - Nakazato, K.

AU - Nishida, A.

AU - Chakihara, H.

AU - Matsuoka, M.

AU - Moniwa, M.

PY - 2004

Y1 - 2004

N2 - A New Vertically Stacked Poly-Si MOSFET has been studied as a novel technique that enables device integration without applying advanced node process. Reduced cell area size of 1.21μm2 has been achieved in 6T-SRAM which is 60% of 130nm node based planer type cell. Operation speed of 533MHz was also confirmed.

AB - A New Vertically Stacked Poly-Si MOSFET has been studied as a novel technique that enables device integration without applying advanced node process. Reduced cell area size of 1.21μm2 has been achieved in 6T-SRAM which is 60% of 130nm node based planer type cell. Operation speed of 533MHz was also confirmed.

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M3 - Conference article

AN - SCOPUS:21644470779

SN - 0163-1918

SP - 923

EP - 926

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - IEEE International Electron Devices Meeting, 2004 IEDM

Y2 - 13 December 2004 through 15 December 2004

ER -

A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAM

Abstract

ASJC Scopus subject areas

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