A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAM

T. Kikuchi, S. Moriya, Y. Nakatsuka, H. Matsuoka, K. Nakazato, A. Nishida, H. Chakihara, M. Matsuoka, M. Moniwa

    Research output: Contribution to journalConference article

    10 Citations (Scopus)

    Abstract

    A New Vertically Stacked Poly-Si MOSFET has been studied as a novel technique that enables device integration without applying advanced node process. Reduced cell area size of 1.21μm2 has been achieved in 6T-SRAM which is 60% of 130nm node based planer type cell. Operation speed of 533MHz was also confirmed.

    Original languageEnglish
    Pages (from-to)923-926
    Number of pages4
    JournalTechnical Digest - International Electron Devices Meeting, IEDM
    Publication statusPublished - 2004 Dec 1
    EventIEEE International Electron Devices Meeting, 2004 IEDM - San Francisco, CA, United States
    Duration: 2004 Dec 132004 Dec 15

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Condensed Matter Physics
    • Electrical and Electronic Engineering
    • Materials Chemistry

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  • Cite this

    Kikuchi, T., Moriya, S., Nakatsuka, Y., Matsuoka, H., Nakazato, K., Nishida, A., Chakihara, H., Matsuoka, M., & Moniwa, M. (2004). A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAM. Technical Digest - International Electron Devices Meeting, IEDM, 923-926.