A new two‐dimensional analysis method for polycrystalline‐silicon tfts

So Yamada, Noriji Kato, Mitsumasa Koyanagi

Research output: Contribution to journalArticlepeer-review

Abstract

A new device simulation method for polycrystal‐line‐silicon thin‐film transistors (denoted as poly‐Si TFTs) is developed. The method is suitable to estimate the TFT characteristics and to analyze the operation mechanisms. In this simulation the influences of grain boundaries are incorporated into the carrier mobility model and the two‐dimensional distributions of the electrostatic potential and carrier concentrations are solved numerically. This simulation has enabled the quantitative evaluation of the dependences of TFT characteristics on grain size and grain boundary trap density, and the current‐voltage characteristics obtained as a result are in good agreement with the measured characteristics over a wide range from the on‐state region to the subthreshold region. Furthermore, in combination with the carrier generation model, high‐field phenomena such as the kink effect and avalanche breakdown can be analyzed in detail. By analyzing the mechanism of short channel effects that are inherent in poly‐Si TFT using this simulator, this effect has been attributed to the accumulation of carriers generated by avalanche in the poly‐Si thin film.

Original languageEnglish
Pages (from-to)48-57
Number of pages10
JournalElectronics and Communications in Japan (Part II: Electronics)
Volume76
Issue number12
DOIs
Publication statusPublished - 1993

Keywords

  • Thin‐film transistor
  • device simulation
  • mobility model
  • polycrystalline silicon
  • short‐channel effect

ASJC Scopus subject areas

  • Physics and Astronomy(all)
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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