Abstract
A new process to fabricate offset-gate thin-film transistors (TFT's) for high-voltage (HV) (i.e., >60 V) large-area applications is demonstrated. In contrast to the conventional method where an additional masking step is applied to mask the channel and the offset regions, the n+ source-drain implant is performed in the new process only after contact is open, and is therefore self-aligned to the contact. The offset-gate transistors are achieved by proper transistor layout where the contact-to-gate distance equals the designed n+-to-gate offset. In addition to saving one masking count as compared with the conventional method, the new implant-through-contact (ITC) method also features a self-aligned field-plate structure and smaller transistor layout area.
Original language | English |
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Pages (from-to) | 347-349 |
Number of pages | 3 |
Journal | IEEE Electron Device Letters |
Volume | 9 |
Issue number | 7 |
DOIs | |
Publication status | Published - 1988 Jul |
Externally published | Yes |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering