A novel capacitance-resistance (CR-) delay circuit technology for high-density DRAM’s has been developed as a method to assure full asynchronicity between memory cell array and peripheral circuits over a wide range of both operating and process conditions, and thus, to realize a fast access time. A unique noise compensation scheme is introduced to the CR-delay circuit to generate a constant delay even under the power supply line noise. This CR-delay circuit was applied to the 4-Mbit DRAM peripheral circuit. As a result, a timing loss as well as a malfunction could be successfully avoided, and 7 ns faster access time and 39 ns shorter cycle time have been achieved, compared with a conventional design using normal inverter chains.
ASJC Scopus subject areas
- Electrical and Electronic Engineering