A New Cell Structure with a Spread Source/Drain (SSD) Mosfet and a Cylindrical Capacitor for 64-Mb Dram’s

Takashi Yamada, Hiroshi Takato, Katsuhiko Hieda, Akihiro Nitayama, Fumio Horiguchi, Fujio Masuoka, Shuichi Samata, Yoshiaki Matsushita

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)

Abstract

A new cell structure to realize a small memory cell size has been developed for 64-Mb DRAM’s. The source/drain regions of a switching transistor are raised by using a selective silicon growth technique. Because of lateral growth of the silicon over gate and field regions, the bitline contact can overlap the gate and field regions. Moreover, the shallow source/drain junction by the raised source/drain structure realizes a reduction of gate length and isolation spacing. As a result, the DRAM memory cell area can be reduced to 37% of that using the conventional LDD MOSFET. In the fabrication of an experimental DRAM cell, a new stacked capacitor structure has been introduced to maintain enough storage capacitance, even in the small-cell area. The new capacitor is made by a simple and unique process using a cylindrical silicon-nitride sidewall layer. It has been verified that this cell structure has the potential to realize multimegabit DRAM’s, such as 64-Mb DRAM’s.

Original languageEnglish
Pages (from-to)2481-2486
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume38
Issue number11
DOIs
Publication statusPublished - 1991 Nov

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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