Abstract
In this paper we propose a new architecture of digital vision chip, in which photo detectors and parallel processing elements designed in digital circuits are integrated together. In this architecture, the function to join several PEs is introduced and summation is calculated at high speed. Also, some sample algorithms and a 64×64 pixels prototype chip we developed will be described.
Original language | English |
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Pages | 266-269 |
Number of pages | 4 |
Publication status | Published - 2002 Dec 1 |
Externally published | Yes |
Event | 2002 Symposium on VLSI Circuits Digest of Technical Papers - Honolulu, HI, United States Duration: 2002 Jun 13 → 2002 Jun 15 |
Other
Other | 2002 Symposium on VLSI Circuits Digest of Technical Papers |
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Country/Territory | United States |
City | Honolulu, HI |
Period | 02/6/13 → 02/6/15 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering