A Neuron-MOS Neural Network Using Self-Learning-Compatible Synapse Circuits

Tadashi Shibata, Hideo Kosaka, Hiroshi Ishii, Tadahiro Ohmi

Research output: Contribution to journalArticlepeer-review

33 Citations (Scopus)

Abstract

A circuit technology for self-learning neural network hardware has been developed using a high-functionality device called Neuron MOS Transistor (νMOS) as a key circuit element. A νMOS can perform weighted summation of multiple input signals and thresholding all at a single transistor level based the charge sharing among multiple capacitors. An electronic synapse cell has been constructed with six transistors by merging a floating-gate EEPROM memory cell into a new-concept νMOS differential-source-follower circuitry. The synapse can represent both positive (excitatory) and negative (inhibitory) weights under single VDD power supply and is free from standby power dissipation. An excellent linearity in the weight updating characteristics of the synapse memory has been also established by employing a simple self-feedback regime in each cell circuitry, thus making it fully compatible to the on-chip self-learning architecture of νMOS neural networks. The basic operation of the synapse cell and a νMOS neural network using the synapse has been experimentally verified using test circuits fabricated by a double-polysilicon CMOS process.

Original languageEnglish
Pages (from-to)913-922
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume30
Issue number8
DOIs
Publication statusPublished - 1995 Aug

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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