A programming technology is proposed to improve the endurance and read retention characteristics of NAND-structured EEPROM cells programmed by Fowler-Nordheim tunneling of electrons. Erasing and writing are accomplished uniformly over the whole channel area instead of nonuniform erasing at the drain. To achieve programming over the whole channel area, a new device structure is also proposed. The high-voltage pulses can be easily generated on a chip from a single 5-V power supply because the direct current due to the avalanche breakdown does not flow. The gate length of the memory transistor is 1.0 μm. Using 1.0 μm rules, the cell size per bit is 11.7 μm 2.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|Publication status||Published - 1990 Dec 1|
|Event||1990 Symposium on VLSI Technology - Honolulu, HI, United States|
Duration: 1990 Jun 4 → 1990 Jun 7
ASJC Scopus subject areas
- Electrical and Electronic Engineering