A multiple-valued reconfigurable VLSI architecture using binary-controlled differential-pair circuits

Xu Bai, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


This paper presents a fine-grain bit-serial reconfigurable VLSI architecture using multiple-valued switch blocks and binary logic modules. Multiple-valued signaling is utilized to implement a compact switch block. A binary-controlled current-steering technique is introduced, utilizing a programmable three-level differential-pair circuit to implement a high-performance low-power arbitrary two-variable binary function, and increase the noise margins in comparison with the quaternary-controlled differential-pair circuit. A current-source sharing technique between a series-gating differential-pair circuit and a current-mode D-latch is proposed to reduce the current source count and improve the speed. It is demonstrated that the power consumption and the delay of the proposed multiple-valued cell based on the binary-controlled current-steering technique and the current-source-sharing technique are reduced to 63% and 72%, respectively, in comparison with those of a previous multiple-valued cell.

Original languageEnglish
Pages (from-to)1083-1093
Number of pages11
JournalIEICE Transactions on Electronics
Issue number8
Publication statusPublished - 2013 Aug


  • Binary-controlled current-steering technique
  • Current-mode logic (CML)
  • Current-source sharing technique
  • Fine-grain reconfigurable VLSI architecture
  • Multiple-valued switch block

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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