A multiple-valued logic array VLSI based on two-transistor delta literal circuit and its application to real-time reasoning systems

Takahiro Hanyu, Yasushi Kojima, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A multiple-valued logic array VLSI for high-speed pattern matching is presented. Both input data and rules are represented by a single multiple-valued digit, so that pattern matching can be described by a multiple-valued delta-literal, in which thresholds correspond to content of a rule. Moreover, a multiple-valued pattern-matching cell can be implemented by only a pair of an NMOS and a PMOS transistors whose threshold voltages are programmed by multiple ion implants. It is demonstrated that the chip area and power dissipation of 8-valued logic array can be reduced to 30% and 50%, respectively, compared with corresponding binary implementation.

Original languageEnglish
Title of host publicationProceedings of The International Symposium on Multiple-Valued Logic
PublisherPubl by IEEE
Pages16-23
Number of pages8
ISBN (Print)0818621451
Publication statusPublished - 1991 May 1
EventProceedings of the 21st International Symposium on Multiple-Valued Logic - Victoria, BC, Can
Duration: 1991 May 261991 May 29

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

OtherProceedings of the 21st International Symposium on Multiple-Valued Logic
CityVictoria, BC, Can
Period91/5/2691/5/29

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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