A multi-pillar vertical metal-oxide-semiconductor field-effect transistor type dynamic random access memory core circuit for sub-1 v core voltage operation without overdrive technique

Hyoungjun Na, Tetsuo Endoh

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

In this paper, a dynamic random access memory (DRAM) core circuit realizing sub-1 V core voltage operation without using the overdriven sense amplifier technique is proposed by using the multi-pillar vertical MOSFET, and its performance is described with the HSPICE simulation. The proposed DRAM core circuit realizes the same sensing time at 0.6 and 0.75 V lower core supply voltage without and with the overdriven sense amplifier technique, respectively, comparing to the conventional DRAM core circuit by the planar MOSFET with the overdriven sense amplifier technique. Moreover, when VCORE is 1.25 V and VDD is 1.5 V, the overdriven proposed sense amplifier achieves 79% (2.7 ns) faster sensing time than the overdriven conventional sense amplifier. Furthermore, the proposed circuit achieves a faster wordline transition and precharge time than the conventional DRAM core circuit by approximately 17% (1.1 ns) and 55% (0.2 ns), respectively. This proposed DRAM core circuit is a promising circuit technique for low voltage and high speed DRAM core circuit operation. copy; 2013 The Japan Society of Applied Physics.

Original languageEnglish
Article number04CE08
JournalJapanese journal of applied physics
Volume52
Issue number4 PART 2
DOIs
Publication statusPublished - 2013 Apr 1

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

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