Abstract
Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause a large overhead in area when a number of contexts are used. To overcome the overhead, a fine-grained MC-FPGA architecture using a floating-gate-MOS functional pass gate (FGFP) is presented which merges threshold operation and storage function on a single floating-gate MOS transistor. The test chip is designed using a 0.35 μm CMOS-EPROM technology. The transistor count of the proposed multi-context switch (MC-switch) is reduced to 13 in comparison with SRAM-based one. The total area of the proposed MC-FPGA is reduced to about 56 of that of a conventional SRAM-based MC-FPGA.
Original language | English |
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Pages (from-to) | 1655-1661 |
Number of pages | 7 |
Journal | IEICE Transactions on Electronics |
Volume | E89-C |
Issue number | 11 |
DOIs | |
Publication status | Published - 2006 Nov |
Keywords
- Bit-serial architecture
- DPGA
- Dynamically reconfigurable architecture
- Time-multiplexed FPGA
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering