A multi-context FPGA using a floating-gate-MOS functional pass-gate and its CAD environment

Masanori Hariyama, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause significant overhead in area and power consumption. To overcome the overhead, a fine-grained MC-FPGA architecture using a floating-gate-MOS functional pass gate(FGFP) is presented which merges threshold operation and storage function on a single floating-gate MOS transistor. The test chip is designed using a 0.35μm CMOS-EPROM technology. The transistor count of the proposed multi-context switch (MC-switch) is reduced to 13% in comparison with SRAM-based one. The total area of the proposed MC-FPGA is reduced to about 56% of that of a conventional SRAM-based MC-FPGA.

Original languageEnglish
Title of host publicationAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Pages1803-1806
Number of pages4
DOIs
Publication statusPublished - 2006 Dec 1
EventAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems - , Singapore
Duration: 2006 Dec 42006 Dec 6

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

OtherAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
CountrySingapore
Period06/12/406/12/6

Keywords

  • Bit-serial architecture
  • DPGA
  • FPGA
  • High-level synthesis

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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